Hybrid current-starved phase-interpolation circuit for...

Details Hybrid current-starved phase-interpolation circuit for... Hybrid current-starved phase-interpolation circuit for...

2007-11-27

2007-11-27

Mis, David (Department: 2817)

Oscillators

Ring oscillators

C327S237000

Reexamination Certificate

active

11369475

ABSTRACT:
A hybrid circuit includes a current-starved voltage-controlled circuit configured to adjust a first type of signal difference, and a phase-interpolated voltage controlled circuit configured to adjust a second type of signal difference. The current-starved circuit and the phase-interpolated circuit cooperate to provide improved operational performance of the hybrid circuit.

REFERENCES:
patent: 5841325 (1998-11-01), Knotts et al.
patent: 6377129 (2002-04-01), Rhee et al.
Ian A. Young, et al., “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”, IEEE Journal of Solid-State Circuits; vol. 27, No. 11, Nov. 1992; pp. 1599-1607.
Jonghae Kim et al., : A 44GHz Differentially Tuned VCO with 4GHz Tuning Range in 0.2um SOI CMOS, ISSCC 2005, Session 22/ PLL, DLL, and VCOs /22.4; 3 pages.
Jafar Savoj et al, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector”, IEEE Journal of Sold-State Circuits, vol. 36, No. 5, May 2001; pp. 761-767.
Woogeun Rhee, “A Low Power, Wide Linear-Range CMOS Voltage-Controlled Oscillator”, IEEE, 1998; pp. 11-85 to 11-88.

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