Hybrid counter with an asynchronous front end

Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Counter controlled counter

Reexamination Certificate

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C377S118000

Reexamination Certificate

active

10954889

ABSTRACT:
Integrated circuit counting apparatuses are described. More particularly, a hybrid counter (203) including an asynchronous counter (310) front end and a synchronous counter (311) back end is described. The asynchronous counter (310) including at least one asynchronous counter stage (341, 342, 343) having an asynchronous level-mode state machine (381, 382). The asynchronous level-mode state machine formed of Differential Cascode Voltage Switch Logic.

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Xilinx, Inc.; “Virtex-II Platform FPGA Handbook”; published Dec. 2000; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 161-183.

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