Hybrid circuit structure fabrication methods using high energy e

Details Hybrid circuit structure fabrication methods using high energy e Hybrid circuit structure fabrication methods using high energy e

1990-02-23

1991-06-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437928, 148DIG46, 430270, H01L 2100, H01L 2102, B05D 300, B05D 302

Patent

active

050249690

ABSTRACT:
A method of fabricating high density multi-chip interconnects whereby one or more polymer layers thereon are cured at approximately room temperature utilizing high energy electron bombardment. The polymer layers, typically in the range of five to twenty microns in thickness, cured in accordance with the present invention, have very low ambiant temperature interlayer stresses, resulting in higher reliability and/or a wider operating temperature range for the finished high density multi-chip interconnect. In addition, curing times are grossly reduced, thereby making the manufacturing processing much more orderly and rapid. Interlayer adhesion of polymer layers cured in accordance with the present invention may be enhanced by the baking of the same at an elevated temperature below the glass transition temperture for the polymer. Various methods and parameters are disclosed.

REFERENCES:
patent: 4130424 (1978-12-01), Feit et al.
patent: 4507333 (1985-03-01), Baise et al.
patent: 4600685 (1986-07-01), Kitakohji et al.
patent: 4740451 (1988-04-01), Kohara

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