Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1998-06-24
2001-04-03
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S019000, C716S030000
Reexamination Certificate
active
06212490
ABSTRACT:
MICROFICHE APPENDIX
The microfiche appendix includes two microfiche with a total number of frames
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A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. of 121.
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuit design, and more particularly to a system and method for analyzing analog characteristics of an integrated circuit design.
DESCRIPTION OF BACKGROUND ART
In designing an integrated circuit chip (source chip), the source chip design effectively must interact with a plurality of integrated circuit chips (target chips), which, like the source chip are electrically coupled to a printed circuit board (PCB)/multi-chip module (MCM). Typically, a conventional analog simulation software tool, such as SPICE, is used to attempt to identify an optimal design for the source chip. Prior to initiating the SPICE simulation, however, the logic design (package) and the input/output (I/O) pin configuration (I/O ring) of each integrated circuit chip as well as the PCB/MCM is transformed into at least one analog circuit model. In addition, input stimuli and specific routes (output circuit blocks) between the I/O ring of the source chip and the I/O ring of the target chips must be defined.
Based upon the SPICE simulation results, the performance of the source chip design can be analyzed and alterations to the source chip design can be made. When the source chip design is altered, a new analog circuit model is generated and a new SPICE simulation is executed. The new performance results again are analyzed and a decision must again be made as to whether the source chip design must be further modified. Prior to finalizing the design of the source chip, several iterations of redesigning and resimulating the source chip design may be performed.
Even though conventional SPICE simulations are relatively helpful for optimizing the performance of the source chip with regard to the PCB/MCM and the target chips, SPICE still possesses certain limitations, which preclude the optimal design of a source chip from truly being realized. Utilizing an ideal analog circuit analysis tool, a conventional system would be able to simulate in its entirety a single integrated analog circuit model, which included the source chip, the target chips and the PCB/MCM. Unfortunately, since conventional analog simulation tools, such as SPICE, can only simulate circuits with approximately 10,000 transistors, typical analog circuit models, which contain well above that number of transistors, cannot be analyzed as a whole. Rather, a conventional system must deconstruct the analog circuit model into smaller discrete sub-components, which each are separately simulated. The results of each of these simulations then are interpolate to determine the overall performance characteristics of the combined analog circuit model, which result in the development of the optimal source chip design. Unfortunately, with interpolative techniques having inherent inaccuracies, the optimal source chip design is not usually fully realized.
Another limitation with simulating a combined analog circuit model is that in addition to not being able to simulate all of the components of an analog circuit model together, the user also cannot solely rely upon SPICE simulations for real-time circuit analysis of certain integrated circuits, such as the target chips. For example, since the source chip often is designed at the same time as the target chips, the attempt to construct an optimal source chip design must be accomplished without full information regarding the target chips. Since SPICE simulations require extensive information concerning the design of the integrated circuit chip, an alternative software simulation tool, which relies upon behavioral circuit models, such as Input/Output (I/O) Buffer Information Specification (IBIS), must be used to approximate the final design of the integrated circuit chips, which have not yet been fully designed.
One such conventional software simulation package, which approximates real-time conditions of IBIS behavioral circuit models, is the BoardQuest by Cadence Design System of San Jose, Calif. Such conventional IBIS-based simulators rely upon an electronic look-up table, rather than upon the physical layout design of the chip, to simulate a behavioral circuit model with specific current and voltage I/O behavioral characteristics. Like SPICE, after an IBIS-based simulator constructs the circuit model, specific input stimuli is defined in order for the output results to be generated. Unlike SPICE, however, the IBIS-based simulator does not directly take into consideration the PCB/MCM. Rather, the focus is upon predefined I/O behavioral characteristics of the target chip. Any PCB/MCM effects upon the source chip or the target chips must be approximated by integrating estimate voltage and current I/O behavioral characteristics into the source chip or the target chip behavioral circuit models. Such rough approximations of the interaction of the PCB/MCM with the source chip and target chips further add to the inaccuracy of the output results of the simulation.
Additionally, as the clock speed of the PCB/MCM increases, the IBIS-based simulator is unable to adequately compensate for the source chip and the target chips becoming more sensitive to noise and timing problems. Should the IBIS-based simulations be attempted at PCB/MCM speeds above approximately 100 MHz, IBIS-based simulations will fail to produce satisfactory results that account for such subtle, but influential analog effects as simultaneous switching noise, ground bounce, signal integrity and timing issues. Furthermore, since IBIS-based circuit models and SPICE circuit models are incompatible, the limitations of IBIS-based simulators cannot be circumvented by utilizing SPICE to simulate IBIS-based behavioral models. Without these subtle high speed analog effects included within the software simulation of the behavioral circuit model, the results of these higher clock speed simulations results in merely idealized results, which do not reflect real-time effects on the source chip.
To ensure more accurate simulation results for designing an optimal source chip, what is needed is a system and method for more accurately simulating the behavioral and analog characteristics of the source chip integrated with the PCB/MCM and the target chips including the timing and noise effects which are attributable to high speed PCB/MCM clock speeds.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method and system for analyzing the operation of a source chip design in conjunction with the PCB/MCM and the target chips through the construction and simulation of a hybrid circuit model. In this manner, the operation of each component of the circuit model, including the source chip and the associated PCB/MCM and target chips, can be jointly observed, measured, and adjusted during the design process of each component.
In order to accomplish such a simulation, it is useful to extract the essential analog characteristics of the PCB/MCM and the source chip and construct a hybrid circuit model framework. A plurality of target chip behavioral models then are integrated with the hybrid circuit model framework to create the hybrid circuit model. A software simulation tool then accurately measures and analyzes the hybrid circuit model for real-time conditions, which will assist in optimizing the source chip.
Unlike previous attempts at analyzing the combined circuit model, the simulation of the hybrid circuit model account for, even at high PCB/MCM clock speeds, the following electrical characteristics: 1) timing effects, including intra- and inter-component delays for various PCB/MCM components, 2) noise effe
Huang Chi-Jung
Li Ken-Ming
Choi Kyle J.
Fenwick & West LLP
S3 Incorporated
Teska Kevin J.
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