Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
1999-07-30
2001-07-17
Wilczewski, Mary (Department: 2811)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S127000, C438S106000
Reexamination Certificate
active
06261869
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to a chip package that utilizes both BGA and QFP lead types, and more particularly to a process and assembly for a hybrid chip package that can accommodate the temperature changes of a high-speed device and how they translate to the package materials and associated printed circuit board.
2. Description of the Related Art
In response to current demands from the electronics industry to produce smaller, faster, and more reliable devices, many semiconductor manufacturers have looked at exploiting the advantages of ball grid array (“BGA”) technology. There are three major types of BGA assemblies in use today primarily differentiated by the substrate type: tape ball grid array (“TBGA”), plastic or laminate ball grid array (“PBGA”) and ceramic ball grid array (“CBGA”).
FIGS. 1A and 1B
show a cross-sectional and a top plan view of a conventional high-speed BGA package
9
A before being attached to a printed circuit board (“PCB”). More specifically, these figures show a BGA substrate
15
having contact wires
17
and a solder bump structure
19
. Contact wires
17
mount between the chip contact terminals
11
A and the substrate contact terminals
15
A. The solder bump structure
19
includes an array of solder bumps
19
A and pads
19
B attached to the bottom surface of the substrate
15
to establish a connection with the contact wires
17
and chip
11
through the substrate
15
. A protective layer
13
, of a material such as an epoxy resin, is deposited to encapsulate the chip
11
, the contact wires
17
, and a portion of the substrate
15
.
Once the above package is attached to a PCB
20
by a known method (see FIG.
2
), the chip can be activated. During operation, the chip
11
will cycle through high and low temperatures which will in turn strain the resultant structure near a peripheral region
21
where the solder balls
19
A contact the PCB contacts. This strain is due to different coefficient of thermal expansion (“CTE”) properties of the assembly. More specifically, the PCB
20
provides a greater CTE change S
1
during operation than the CTE change S
2
provided by the package. These strains induce the BGA joints to flake
19
C and crack
19
D as illustrated in FIG.
2
.
Currently, the chip package of choice for high-speed or signal integrity is the ceramic flip chip, such as an SRAM chip package on a 1 inch ceramic substrate having a ball grid array (“BGA”) structure containing up to 300 solder balls with a pitch of about 1.27 mm. This chip reaches operational temperatures between about 27 and 110 degrees Celsius. Unfortunately, as mentioned above this type of chip package has a tendency to fail during operation because of its excessive thermal cycling properties. More specifically, the differences in the CTE between the ceramic package and the fiberglass/resin PCB assembly causes excessive strain on the BGA pins at the edges of the chip during operational cycles. Consequently, the BGA joints flake or crack to form electrical opens making the package unreliable and ineffective.
The magnitude of the operational strain on the BGA pins depends on the geometry of the chip, the temperature difference and the CTE's of the materials involved.
The operating temperature of a given chip depends on its function, signal speed and technology. As performance increases and chip size decreases, temperatures tend to follow. It is very difficult to keep chips operating at a low temperature. The materials can be changed at a price. Exotic board materials with smaller CTE's (closer to ceramics) are available. However, they do not have the track record of success that conventional FR4 board materials. In turn, their electrical properties are so different, that board designs have to be adjusted for them. Given the current focus on keeping costs low, this is an unattractive option.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a semiconductor device assembly is provided for reducing the development of electrical opens created during operational cycles. More specifically, the present invention provides a semiconductor chip; a ball grid array (“BGA”) structure; a substrate coupled between the chip and the BGA structure; a plurality of quad flat panel (“QFP”) leads coupled to said substrate; and a protective layer bonded to an over the chip and a portion of the substrate adjacent the chip.
In another aspect of the instant invention, a process is provided for fabricating a semiconductor device. More specifically, the process includes the steps of providing a substrate including first and second surfaces; attaching a plurality of quad flat panel (“QFP”) leads to the substrate on a first surface; securing a semiconductor chip to a second surface of the substrate; encapsulating the chip and a portion of the substrate adjacent the chip; and coupling a ball grid array (“BGA”) structure to the substrate on the first surface.
In still another aspect of the instant invention provides a chip package assembly. More specifically, the present assembly includes a semiconductor chip; a ball grid array (“BGA”) structure; a substrate coupled between the chip and the BGA structure; a protective layer encapsulating the chip and a portion of the substrate adjacent the chip; and a plurality of conductive leads electrically coupled between the assembly and PCB that provide a flexible characteristic for accommodating the physical changes that the resultant structure endures during operational cycles.
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patent: 5563446 (1996-10-01), Chia
patent: 5569955 (1996-10-01), Chillara
patent: 5693980 (1997-12-01), Sugahara
patent: 5705851 (1998-01-01), Mostafazadeh
patent: 5777387 (1998-07-01), Yamashita
patent: 5789811 (1998-08-01), Chia
patent: 5969426 (1999-10-01), Baba
patent: 6022759 (2000-02-01), Seki
patent: 6031281 (2000-02-01), Kang
patent: 6071755 (2000-06-01), Baba
D'Amato Gerald J.
Radford Susan K.
Goodwin David
Hewlett--Packard Company
Wilczewski Mary
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