Hybrid analog-to-digital converter (ADC) with...

Details Hybrid analog-to-digital converter (ADC) with... Hybrid analog-to-digital converter (ADC) with...

2009-06-12

2010-10-12

Mai, Lam T (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

07812757

ABSTRACT:
A hybrid Analog-to-Digital Converter (ADC) has a binary-weighted capacitor array and a sub-voltage capacitor array that are coupled together by a coupling capacitor. The sub-voltage capacitor array uses a minimum capacitor size that matches the minimum capacitor size of the binary-weighted capacitor array. The coupling capacitor is double the minimum size and reduces a voltage effect on a charge sharing line by half. Second coupling capacitors in the sub-voltage capacitor array each reduce the voltage effect by half, so that first, second, and third sub-voltage capacitors in the sub-voltage capacitor array produce ½, ¼, and ⅛ voltage swings using the minimum size capacitance. Only MSB capacitors in the binary-weighted capacitor array sample the analog input voltage. During conversion, MSB's from a Successive-Approximation-Register (SAR) are applied to binary-weighted capacitors while LSB's are applied to sub-voltage capacitors. The total capacitance is reduced by applying the LSB's only to the sub-voltage capacitor array.

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Alpman et al. “A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS”, ISSCC 2009 / Session 4 / High-Speed Data Converters / 4.2, Feb. 9, 2009.

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