Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
1999-01-20
2001-01-09
Rosasco, S. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
Reexamination Certificate
active
06171731
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to simulation of an aerial image, and particularly relates to simulation of an aerial image produced by a mask to be used in patterning an integrated circuit (IC) chip during semiconductor wafer fabrication.
2. Description of the Related Art
A. Wafer Construction
Photolithography is a common technique employed in the manufacture of semiconductor devices. Typically, a semiconductor wafer is coated with a layer (film) of light-sensitive material, such as photoresist. Using a patterned mask or reticle, the wafer is exposed to projected light, typically actinic light, which manifests a photochemical effect on the photoresist, which is subsequently chemically etched, leaving a pattern of photoresist “lines” on the wafer corresponding to the pattern on the mask.
A “wafer” is a thin piece of semiconductor material from which semiconductor chips are made. The four basic operations utilized to fabricate wafers include (1) layering, (2) patterning, (3) doping and (4) heat treatments.
The layering operation adds thin layers of material, including insulators, semiconductors, and conductors, to a wafer surface. During the layering operation, layers are either grown or deposited. Oxidation involves growing a silicon dioxide (an insulator) layer on a silicon wafer. Deposition techniques include, for example, chemical vapor deposition, evaporation, and sputtering. Semiconductors are generally deposited by chemical vapor deposition, while conductors are generally deposited with evaporation or sputtering.
Patterning involves the removal of selected portions of surface layers. After material is removed, the wafer surface has a pattern. The material removed may form a hole or an island. The process of patterning is also known to those skilled in the relevant art as microlithography, photolithography, photomasking and masking. The patterning operation serves to create parts of the semiconductor device on the wafer surface in the dimensions required by the circuit design and to locate the parts in their proper location on the wafer surface.
Doping involves implanting dopants in the surface of the wafer through openings in the layers to create the n-type and p-type pockets needed to form the N-P junctions for operation of discrete elements such as transistors and diodes. Doping is generally achieved with thermal diffusion (the wafer is heated and exposed to the desired dopant) and ion implantation (dopant atoms are ionized, accelerated to high velocities and implanted into the wafer surface).
Construction of semiconductor wafers with these steps is well known in the art of semiconductor fabrication. Examples of wafer construction processes are described in U.S. Pat. No. 5,679,598 issued to Yee on Oct. 21, 1997, entitled “Method of Making a CMOS Dynamic Random-Access Memory (DRAM),” U.S. Pat. No. 5,663,076 issued to Rostoker et al. on Sep. 2, 1997, entitled “Automating Photolithography in the Fabrication of Integrated Circuits,” U.S. Pat. No. 5,595,861 issued to Garza on Jan. 21, 1997, entitled “Method of Selecting and Applying a Top Antireflective Coating of a Partially Fluorinated Compound,” U.S. Pat. No. 5,444,265 issued to Hamilton on Aug. 22, 1995, entitled “Method and Apparatus for Detecting Defective Semiconductor Wafers During Fabrication Thereof,” and U.S. Pat. No. 4,652,134 issued to Pasch et al. on Mar. 24, 1987, entitled “Mask Alignment System.” The specifications of these five patents identified in this paragraph are hereby incorporated herein as though set forth in full by this reference.
B. Patterning And Proximity Effects
One of the most critical operations in wafer fabrication, patterning sets the dimensions of the electronic devices to be implemented on the IC chip. Errors in the patterning process can cause distortions that cause changes in the functions of these electronic devices.
Design rule limitations frequently are referred to as critical dimensions. A critical dimension of a circuit is commonly defined as the smallest width of a line or the smallest space between two lines. Consequently, the critical dimension determines the overall size and density of an IC. In present IC technology, the smallest critical dimension for state-of-the-art circuits is 0.3 micron for line widths and spacings.
Once the layout of the circuit has been created, the next step to manufacturing the integrated circuit is to transfer the layout onto a semiconductor substrate. Photolithography is a well known process for transferring geometric shapes present on a mask onto the surface of a silicon wafer. In the field of IC lithographic processing, a photosensitive polymer film called photoresist is normally applied to a silicon substrate wafer and then allowed to dry. An exposure tool is utilized to expose the wafer with the proper geometrical patterns through a mask (or reticle) by means of a source of light or radiation. After exposure, the wafer is treated to develop the mask images transferred to the photosensitive material. These masking patterns are then used to create the device features of the circuit.
FIG. 1A
is a functional block diagram illustrating a system for patterning an IC chip
26
using a mask
22
. Referring to
FIG. 1
, light
21
is incident on mask
22
at a right angle. Such would be the case for a single point light source directly above mask
22
and far enough from mask
22
so that the wavefront at mask
22
would be approximately planar. It should, however, be noted that light
21
is shown in this manner for illustration purposes only. Generally, the light source will be an extended body consisting of many different points and, accordingly, light generally will strike mask
22
at many different angles. Thus, as shown in
FIG. 1B
, the light from points
31
and
32
on light source
30
will strike mask
35
at different angles.
Mask
22
includes transmissive and non-transmissive portions which effectively transmit and block light
21
so as to produce the desired pattern on IC chip
26
. The light
23
exiting from mask
22
passes through optical system
24
and, finally, contacts IC chip
26
, forming a light intensity pattern. Often, optical system
24
merely comprises the distance between mask
22
and IC chip
26
. However, optical system
24
may include one or more lenses, mirrors and/or other optical elements.
An important limiting characteristic of the exposure tool is its resolution value. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose onto the wafer. Currently, the resolution for most advanced optical exposure tools is around 0.2 micron. Thus, the resolution value of present lithographic equipment is close to the critical dimension for most IC circuit designs. Consequently, the resolution of the exposure tool may influence the final size and density of the IC circuit. As the critical dimensions of the layout become smaller and approach the resolution value of the lithographic equipment, the consistency between the masked and actual layout pattern developed in the photoresist is significantly reduced. Specifically, it is observed that differences in pattern development of circuit features depends upon the proximity of the features to one another.
The magnitude of such proximity effects depends on the proximity or closeness of the two features present on the masking pattern. Proximity effects are known to result from optical diffraction in the projection system. This diffraction causes adjacent features to interact with one another in such a way as to produce pattern-dependent variations.
Proximity effects and methods for correcting for them (i.e., optical proximity correction, or OPC, methods) are discussed in U.S. Pat. No. 5,682,323 issued on Oct. 28, 1997, to Pasch et al. entitled “System and Method for Performing Optical Proximity Correction on Macrocell Libraries” (hereinafter the “Pasch '323 patent”). The specification of the Pasch '323 patent is incorporated herein as though set forth in full by
Medvedeva Marina G.
Petranovic Dusan
Scepanovic Ranko
LSI Logic Corporation
Rosasco S.
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