Huffman decoding method, circuit and system employing conditiona

Details Huffman decoding method, circuit and system employing conditiona Huffman decoding method, circuit and system employing conditiona

1993-11-30

1995-12-26

Young, Brian K.

Coded data generation or conversion

Digital code to digital code converters

To or from number of pulses

H03M 740

Patent

active

054791669

ABSTRACT:
This invention decodes a continuous stream of Huffman encoded data, each datum having a size portion of a predetermined number of bits and a value portion of a variable number of bits. The invention extracts the size portion, determines the variable number of bits of the value portion and extracts this value portion. The decoding of this value portion differs depending upon the sign bit. If this sign bit is "1", then translation is required. A mask constant having a single "1" bit is rotated an amount equal to the size aligning this single "1" bit with the most significant bit of the value portion. This rotated mask is ANDed with the value portion. A zero result indicates no translation is needed. The translation, if needed, takes place by subtraction. The quantity 2.sup.N -1 is subtracted from the value portion, where N is the size. A mask generator (239) forms the quantity 2.sup.N -1 by forming a number of right justified "1's" equal to the size. In the preferred embodiment a data processing apparatus (71, 72, 73, 74) having an arithmetic logic unit (230) with a barrel rotator (235) and a mask generator (239) performs the key steps of the decoding. In the preferred embodiment of this invention, the arithmetic logic unit (230) is embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.

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Microprocessor Report, Slater, Michael, "IIT Ships Programmable Video Processor," vol. 5, No. 20, Oct. 30, 1991 pp. 1, 6-7, 13.

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