Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Target device
Reexamination Certificate
2001-11-09
2008-12-09
Phan, Thai (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Target device
C703S025000, C703S027000, C709S223000, C710S302000
Reexamination Certificate
active
07464016
ABSTRACT:
In one embodiment, a distributed simulation system may include a first node configured to participate in a simulation and a second node configured to transmit a hot pull command designating the first node. The first node does not participate in the simulation responsive to the hot pull command. In another embodiment, A distributed simulation system may include a first node configured to participate in a simulation and a second node configured to transmit a hot plug command designating the first node. The first node does not participate in the simulation prior to the hot plug command. Additionally, the first node begins participation in the simulation responsive to the hot plug command.
REFERENCES:
patent: 4456994 (1984-06-01), Segarra
patent: 4590581 (1986-05-01), Widdoes, Jr.
patent: 4821173 (1989-04-01), Young et al.
patent: 4937173 (1990-06-01), Kanda et al.
patent: 5185865 (1993-02-01), Pugh
patent: 5247650 (1993-09-01), Judd et al.
patent: 5317693 (1994-05-01), Cuenod et al.
patent: 5327361 (1994-07-01), Long et al.
patent: 5339435 (1994-08-01), Lukin et al.
patent: 5398317 (1995-03-01), Nugent
patent: 5442772 (1995-08-01), Childs et al.
patent: 5455928 (1995-10-01), Herlitz
patent: 5466200 (1995-11-01), Ulrich et al.
patent: 5519848 (1996-05-01), Wloka et al.
patent: 5625580 (1997-04-01), Read et al.
patent: 5634010 (1997-05-01), Ciscon et al.
patent: 5640546 (1997-06-01), Gopinath et al.
patent: 5715184 (1998-02-01), Tyler et al.
patent: 5732247 (1998-03-01), Dearth et al.
patent: 5751941 (1998-05-01), Hinds et al.
patent: 5794005 (1998-08-01), Steinman
patent: 5812824 (1998-09-01), Dearth et al.
patent: 5838948 (1998-11-01), Bunza
patent: 5848236 (1998-12-01), Dearth et al.
patent: 5850345 (1998-12-01), Son
patent: 5870585 (1999-02-01), Stapleton
patent: 5870588 (1999-02-01), Rompaey et al.
patent: 5875179 (1999-02-01), Tikalsky
patent: 5881267 (1999-03-01), Dearth et al.
patent: 5889954 (1999-03-01), Gessel et al.
patent: 5892957 (1999-04-01), Normoyle et al.
patent: 5893155 (1999-04-01), Cheriton
patent: 5907685 (1999-05-01), Douceur
patent: 5907695 (1999-05-01), Dearth
patent: 5910903 (1999-06-01), Feinberg et al.
patent: 5973638 (1999-10-01), Robbins et al.
patent: 5991533 (1999-11-01), Sano et al.
patent: 6031987 (2000-02-01), Damani et al.
patent: 6053947 (2000-04-01), Parson
patent: 6117181 (2000-09-01), Dearth et al.
patent: 6134234 (2000-10-01), Kapanen
patent: 6188975 (2001-02-01), Gay
patent: 6282596 (2001-08-01), Bealkowski et al.
patent: 6289398 (2001-09-01), Stallmo et al.
patent: 6292931 (2001-09-01), Dupenloup
patent: 6345242 (2002-02-01), Dearth et al.
patent: 6393588 (2002-05-01), Hsu et al.
patent: 6449732 (2002-09-01), Rasmussen et al.
patent: 6470397 (2002-10-01), Shah et al.
patent: 6507809 (2003-01-01), Yoshino et al.
patent: 6539520 (2003-03-01), Tiong et al.
patent: 6625650 (2003-09-01), Stelliga
patent: 6628287 (2003-09-01), Duda et al.
patent: 6711411 (2004-03-01), Ruffini
patent: 6711645 (2004-03-01), Chari et al.
patent: 6748451 (2004-06-01), Woods et al.
patent: 6880086 (2005-04-01), Kidder et al.
patent: 6915253 (2005-07-01), Chapman
patent: 7010607 (2006-03-01), Bunton
patent: 7185077 (2007-02-01), O'Toole et al.
patent: 2002/0138242 (2002-09-01), Wilensky et al.
patent: 2002/0188910 (2002-12-01), Zizzo
patent: 2003/0005200 (2003-01-01), Kumar et al.
patent: 2003/0037128 (2003-02-01), Beadles et al.
patent: 2003/0056182 (2003-03-01), Rosenbaum et al.
patent: 2003/0074177 (2003-04-01), Bowen
patent: 2003/0093252 (2003-05-01), Fankel et al.
patent: 2003/0093253 (2003-05-01), Freyensee et al.
patent: 2003/0093254 (2003-05-01), Frankel et al.
patent: 2003/0093255 (2003-05-01), Freyensee et al.
patent: 2003/0093256 (2003-05-01), Cavanagh et al.
patent: 2003/0093569 (2003-05-01), Sivier et al.
patent: 2005/0066087 (2005-03-01), Wu
“Rule Base Driven Conversion of an Object Oriented Design Structure Into Standard Hardware Description Languages,” Verschueren, A.C., IEEE Xplore, appears in Euromicro Conference, 1998, Proceedings. 24th, vol. 1, Aug. 25, 1998, pp. 42-45.
“Modeling Communication with Objective VHDL,” Putzke, et al., IEEE Xplore, appears in Verilog HDL Conference and VHDL International Use Forum, 1998, IVC/VIUF, Proceedings., 1998 International, Mar. 16, 1998, pp. 83-89.
“A Procedural Language Interface for VHDL and its Typical Applications,” Martinolle, et al., IEEE Xplore, appears in Verilog HDL Conference and VHDL International Use Forum, 1998, IVC/VIUF, Proceedings., 1998 International, Mar. 16, 1998, pp. 32-38.
“The Verilog Procedural Interface for the Verilog Hardware Description Language,” Dawson, et al., IEEE Xplore, appears in Verilog HDL Conference, 1996, Proceedings., 1996 International, Feb. 26, 1996, pp. 17-23.
“An Integrated Environment for HDL Verification,” York, et al., IEEE Xplore, appears in Verilog HDL Conference, 1995, Proceedings., 1995 International, Mar. 27, 1995, pp. 9-18.
“The PowerPC 603 C++ Verilog Interface Model,” Voith, R.P., IEEE Xplore, appears in Compcon Spring '94, Digest of Papters, Feb. 28, 1994, pp. 337-340.
Networked Object Oriented Verification with C++ and Verilog, Dearth, et al., IEEE, XP-002144328, 1998, 4 pages.
Patent Abstracts of Japan, publication No. 10326835, published Dec. 8, 1998.
Patent Abstracts of Japan, publication No. 10049560, published Feb. 20, 1998.
Patent Abstracts of Japan, publication No. 10340283, published Dec. 22, 1998.
Patent Abstracts of Japan, publication No. 07254008, published Oct. 3, 1995.
“Multiprocessing Verilog Simulator Exploits the Parallel Nature of HDLs.” Lisa Maliniak, Electronic Design, Abstract, May 30, 1994, 1 page.
“It's A Multithreaded World, Part I,” Charles J. Northrup, BYTE, May 1992, 7 pages.
“It's Multithreaded World, Part 2,” Charles J. Northrup, BYTE, Jun. 1992, pp. 351-356.
“Weaving a Thread,” Shashi Prasad, BYTE, Oct. 1995, pp. 173-174.
“Making Sense of Collaborative Computing,” Mark Gibbs, Network World Collaboration, Jan. 10, 1994, 4 pages.
“Parallel Logic Simulation of VLSI Systems,” Bailey, et al., ACM Computing Surveys, vol. 26, No. 3, Sep. 1994, pp. 255-294.
“Multithreaded Languages for Scientific and Technical Computing,” Cherri M. Pancake, Proceedings of the IEEE, vol. 81, No. 2, Feb. 1993, pp. 288-304.
“Distributed Simulation Architecture, SW Environment, Enterprise Server Products,” Purdue EP400 Presented by Freyensee and Frankel, Nov. 9, 2000, 13 pages.
“BNF and EBNF: What Are They And How Do They Work?,” Lars Marius Garshol, Oct. 12, 1999, pp. 1-10.
“VCK: Verilog-C Kernel,” Testbench Automation, Distribution by Verilog Simulation, Hardware-Software Co-verification, 2001 Avery Design Systems, Inc., 8 pages.
“Principles of Verilog PLI,” Swapnajit Mittra, Silicon Graphics Incorporated, 1999, 10 pages.
“IEEE Standard Hardware Description Language Based on the Verilog® Hardware Description Language,” IEEE, Dec. 12, 1995, 8 pages.
“OpenVera 1.0, Language Reference Manual,” Version 1.0, Mar. 2001, pp. 4-1 to 4-34, pp. 5-1 to 5-32, 6-1 to 6-22, 7-1 to 7-24, 11-1 to 11-50, 12-1 to 12-8, 13-1 to 13-14, 14-1 to 14-20, 15-1 to 15-118.
“VLSI Designe of a Bust Arbitration Module for the 68000 Series of Microprocessors,” Ososanya, et al., IEEE, 1994, pp. 398-402.
“A VHDL Standard Package for Logic Modeling,” David R. Coelho, IEEE Design & Test of Computers, vol. 7, Issue 3, Jun. 1990, pp. 25-32.
“Corrected Settling Time of the Distributed Parallel Arbiter,” M.M. Taub, PhD., IEEE Proceedings, Part E: Computers & Digitals, vol. 139, Issue 4, Jul. 1992, pp. 348-354.
Jerry Banks, ed.; Handbook of Simulation; 1998; John Wiley & Sons, Inc.; pp. 3-51.
Robert W. Sebesta, Concepts of Programming Language, 1999 Addison Wesley L9ongman, Inc., Fourth Edition, pp. 105-131.
Lee, K.C., “A Virtual Bus Architecture for Dynamic Parall
Cavanagh Carl
Frankel Carl B.
Freyensee James P.
Sivier Steven A.
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Phan Thai
Sun Microsystems Inc.
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