Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Reexamination Certificate
2007-10-04
2010-11-16
Phan, Thai (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
C703S014000, C703S017000, C717S124000, C324S719000
Reexamination Certificate
active
07835890
ABSTRACT:
The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described. To further improve the circuit reliability simulation, a gradual or multi-step aging is used instead of the standard one step aging process. Many of these features can be embedded within the circuit simulator. A user data interface is also presented to implement these techniques and further allow users to enter their device models not presented in the simulator. For example, a proprietary model of, say, the substrate current in an NMOS could used be with a SPICE simulator employing a different model to simulate the aging of the circuit.
REFERENCES:
patent: 5533197 (1996-07-01), Moran et al.
patent: 5600578 (1997-02-01), Fang et al.
patent: 5600844 (1997-02-01), Shaw et al.
patent: 5606518 (1997-02-01), Fang et al.
patent: 5615377 (1997-03-01), Shimizu et al.
patent: 5634001 (1997-05-01), Mittl et al.
patent: 5761481 (1998-06-01), Kadoch et al.
patent: 5974247 (1999-10-01), Yonezawa
patent: 6024478 (2000-02-01), Yamamoto
patent: 6047247 (2000-04-01), Iwanishi et al.
patent: 6058496 (2000-05-01), Gillis et al.
patent: 6209122 (2001-03-01), Jyu et al.
patent: 6216099 (2001-04-01), Fang et al.
patent: 6278964 (2001-08-01), Fang et al.
patent: 6363515 (2002-03-01), Rajgopal et al.
patent: 6414498 (2002-07-01), Chen
patent: 6498515 (2002-12-01), Kawakami et al.
patent: 6524872 (2003-02-01), Cheung
patent: 6530064 (2003-03-01), Vasanth et al.
patent: 6795802 (2004-09-01), Yonezawa et al.
patent: 7003755 (2006-02-01), Pang et al.
patent: 7292968 (2007-11-01), Wu et al.
patent: 7567891 (2009-07-01), Liu et al.
patent: 2003/0055621 (2003-03-01), Wu et al.
patent: 2003/0158713 (2003-08-01), Akimoto et al.
Karam, Medhat, et al., “Implmentation of Hot-Carrier Reliability Simulation in Eldo” and related Internet material, Deep Submicron Technical Publication, dated Sep. 2000.
Lou, Choon-Leong, et al., “A Novel Single-Device DC Method for Extraction of the Effective Mobility and Source-Drain Resistances of Fresh and Hot-Carrier Degraded Drain-Engineered MOSFET's”, IEEE Transactions on Electron Devices, vol. 45. No. 6, Jun. 1998, pp. 1317-1323.
Wong, H., et al., “Simulation of Hot-Carrier Reliability in MOS Integrated Circuits”, PROC. 21stInternational Conference on Microelectronics, vol. 2, NIS, Yugoslavia, Sep. 14-17, 1997, pp. 625-628.
Hwang, Nam, et al., “Hot-Carrier Induced Series Resistance Enhancement Model (HISREM) of nMOSFET'S for Circuit Simulations and Reliability Projections”, Microelectronics and Reliability, vol. 35, No. 2, pp. 225-239, Feb. 1995, pp. 225-239.
Aur, S., et al., “Modeling of Hot Carrier Effects for LDD Mosfets”, 1985 Symposium of VLSI Technology, pp. 112-113.
Jiang, Wenjie, et al., “Key Hot-Carrier Degradation Model Calibration and Verification Issues for Accurate AC Circuit-Level Reliability Simulation”, IEEE, 1997, pp. 300-306.
Li et al., “A Probabilistic Timing Approach to Hot-Carrier Effect Estimation,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 10, Oct. 1994, pp. 1223-1234.
IsSpice4 User's Guide,Intusoft, 1988-1996, pp. 196-216.
Kawakami et al., “Gate-Level Aged Timing Simulation Methodology for Hot-Carrier Reliability Assurance,” Proceedings of the ASP-DAC 2000, Asia and South Pacific, Jan. 25-28, 2000, pp. 289-294.
Ye et al., “Developing Aged SPICE Model for Hot Carrier Reliability Simulation,” Integrated Reliability Workshop Final Report, 2000, IEEE International, Oct. 23-26, 2000, pp. 153-154.
Hu, “Simulating Hot-Carrier Effects on Circuit Performance,”Semicond. Sci. Technol.7 (1992) B555-B558.
Wu et al., “Full-Chip Reliability Simulation for VDSM Integrated Circuits,”Microelectronics Reliability41 (2001) pp. 1273-1278.
Seo et al., “The Hot Carrier Degradation and Device Characteristics with Variation of Pre-Metal Dielectric Materials,”Mat. Res. Soc. Symp. Proc., vol. 544, 1999, pp. 179-184.
Kim et al., “Oxide Field Dependence of the NMOS Hot-Carrier Degradation Rate and Its Impact an AC-Lifetime Prediction,” IEEE, 1995, pp. 37-40.
Chen et al., “Statistical Variation of NMOSFET Hot Carrier Lifetime and Its Impact on Digital Circuit Reliability,”IEEE, pp. 29-32, 1995.
Chen et al., “A Unified Compact Scalable Model for Hot Carrier Reliability Simulation,”IEEE, 1999, pp. 243-248.
Kuo, et al., “Simulation of MOSFET Lifetime under AC Hot-Electron Stress,”IEEE Transactions on Electron Devices, vol. 35, No. 7, Jul. 1988, pp. 1004-1011.
Leblebici et al., “An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis,”Proceeding ICCAD, IEEE, 1990, pp. 400-403.
Quader et al., “Hot-Carrier-Reliability Design Rules for Translating Device Degradation to CMOS Digital Circuit Degradation,”IEEE Transactions on Electron Devices, vol. 41, No. 4, May 1994, pp. 681-691.
Hu, C., “Invited Paper Gate Oxide Scaling Limits and Projection,” IEEE, 1996, pp. 13.1.1-13.1.4.
Hu, Chenming, “IC Reliability Simulation”, IEEE Journal of Solid-State Circuits, vol. 27, No. 3, Mar. 1992, pp. 241-246.
Ling, C.H., et al., “Simulation of Logarithmic Time Dependence of Hot Carrier Degradation in PMOSFETs”, Semicond. Sci. Technol. 10, 1995, pp. 1659-1666.
Jiang, Wenjie, et al., “Assessing Circuit-Level Hot-Carrier Reliability”, IEEE, 1998, pp. 173-179.
Li, Chester C., et al., “A New Bi-directional PMOSFET Hot-Carrier Degradation Model for Circuit Reliability Simulation”, IEEE, 1992, pp. 20.7.1-20.7.4.
Quader, Khandker N., et al., “A Bidirectional NMOSFET Current Reduction Model for Simulation of Hot-Carrier-Induced Circuit Degradation”, IEEE Transactions on Electron Devices, vol. 40, No. 12, Dec. 1993, pp. 2245-2254.
Hsu, Wen-Jay, et al., Advanced Integrated-Circuit Reliability Simulation Including Dynamic Stress Effects, IEEE Journal of Solid-State Circuits, vol. 27, No. 3, Mar. 1992, pp. 247-257.
Chang, Steve S., et al., “A New MOSFET Hot Carrier Model in SPICE Feasible for VLSI Reliability Anaylsis”, International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, R.O.C., May 22-24, 1991, pp. 283-287.
Chen Alvin I.
Choi Jeong Y.
Liu Zhihong
McGaughy Bruce W.
Wu Lifeng
Cadence Design Systems Inc.
Chan Thomas
Phan Thai
Wheelock Chan LLP
LandOfFree
Hot carrier circuit reliability simulation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hot carrier circuit reliability simulation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hot carrier circuit reliability simulation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4251761