Host to FPGA interface in an in-circuit emulation system

Details Host to FPGA interface in an in-circuit emulation system Host to FPGA interface in an in-circuit emulation system

2007-04-17

2007-04-17

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Emulation

Of peripheral device

C703S027000, C712S227000, C710S010000, C716S030000

Reexamination Certificate

active

09975105

ABSTRACT:
A multi-purpose interface between a host computer and an FPGA. This interface uses an IEEE 1284 compliant EPP mode connection. When the host computer is initialized, a reset of the FPGA is carried out to clear the configuration memory of the FPGA. The data lines of the interface are then used to communicate unidirectional configuration data into the FPGA. The data are clocked by the host computer using the data strobe signal line to clock data into the FPGA. When the FPGA has been fully programmed, including programming an IEEE 1284 compliant EPP mode interface into the FPGA, the data lines are used for bidirectional communication between the host computer and the configured FPGA, in this embodiment operating as a virtual microcontroller.

REFERENCES:
patent: 5202687 (1993-04-01), Distinti
patent: 5691898 (1997-11-01), Rosenberg et al.
patent: 5802290 (1998-09-01), Casselman
patent: 6034538 (2000-03-01), Abramovici
patent: 6058263 (2000-05-01), Voth
patent: 6144327 (2000-11-01), Distinti et al.
patent: 6460172 (2002-10-01), Insenser Farre et al.
patent: 6816544 (2004-11-01), Bailey et al.
patent: 6967960 (2005-11-01), Bross et al.
patent: 2002/0116168 (2002-08-01), Kim
patent: 2002/0156885 (2002-10-01), Thakkar
patent: 2002/0156998 (2002-10-01), Casselman
Bursky, “FPGA Combines Multiple Interfaces and Logic,” Electronic Design, vol. 48, No. 20, pp. 74-78 (Oct. 2, 2000).
Anonymous, “Warp Nine Engineering—The IEEE 1284 Experts—F/Port Product Sheet,” undated web page found at http://www.fapo.com/fport.htm.
Anonymous, “F/Port: Fast Parallel Port for the PC: Installation Manual: Release 7.1,” circa 1997, available for downloaded from http://www.fapo.com/fport.htm.
CYPR-CD00182; “In-System Chip Emulator Architecture”; Oct. 10, 2001; U.S. Appl. No. 09/975,115; Snyder et al.
CYPR-CD00183; “Capturing Test/Emulation and Enabling Real-Time Debugging Using FPGA for In-Circuit Emulation”; Oct. 10, 2001; U.S. Appl. No. 09/975,104; Snyder.
CYPR-CD00185; “Emulator Chip-Board Architecture and Interface”; Oct. 1, 2001; U.S. Appl. No. 09/975,030; Snyder et al.
CYPR-CD00186“Method for Breaking Execution of Execution of Test Code in a Dut and Emulator Chip Essentially Simultaneously and Handling Complex Breakpoint Events”; Oct. 10, 2001; U.S. Appl. No. 09/975,338; Nemeck et al.

Affiliated with

Also associated with

Rating

Host to FPGA interface in an in-circuit emulation system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Host to FPGA interface in an in-circuit emulation system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Host to FPGA interface in an in-circuit emulation system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3721730