Host register interface testing on bit stream based systems

Details Host register interface testing on bit stream based systems Host register interface testing on bit stream based systems

1999-12-20

2001-10-09

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010

Reexamination Certificate

active

06300770

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the field of bit stream based systems and more particularly to an automated system for host register interface testing.
2. Description of the Relevant Art
Comprehensive verification of host register interfaces provided by programmable chips is a difficult task that is consuming an increasing amount of resources with the advent of increasingly complex system-on-a-chip style application specific integrated circuits (ASIC's). These ASICs may include a large number of programmable operation modes available through a set of host registers. Traditionally, a set of separate tests has been crafted to verify each feature or operating mode of a device independently. Typically, a test template source code is used as a starting point. The various tests are then generated by modifying appropriate parameters in the template source code. Unfortunately, this traditional approach requires a time consuming recompilation of source code each time a new test is to be run. This results in a large number of test programs that have to be executed sequentially to achieve adequate verification coverage of the host register interface. In addition, the process must be repeated for each new revision of a device to ensure compatibility with previous versions. Because this traditional approach to verification is a time consuming process, it would be desirable to implement a system that generated the required test cases automatically.
SUMMARY OF THE INVENTION
The identified problem is addressed in large part by a programmable interface testing system and a related method and computer readable medium. The system includes a host register unit including information that is indicative of a set of host registers corresponding to a programmable device under test. The system further includes a rule set unit including information that is indicative of constraints on values that the set of host registers may assume and a test setup generator configured to access the host register unit and the rule set unit and to generate a set of test setups based on the contents of the host register unit and the rule set unit where each test setup corresponds to a valid state of the set of host registers. In one embodiment, the test setup generator is suitable for applying a test setup from the set of test setups to the device under test. In one embodiment, the system may further include a verifier configured to receive the output of the device under test and, based thereon, for determining the functionality of the device under test. The verifier is preferably adapted to record the functionality determination as well as the test setup generator in a test results log.


REFERENCES:
patent: 4637020 (1987-01-01), Schinabeck
patent: 5589777 (1996-12-01), Davis et al.

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