1995-06-07
1998-11-17
Auve, Glenn A.
G06F 1300
Patent
active
058389342
ABSTRACT:
A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.
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Boutaud Frederic
Chishtie Mansoor A.
Couvrat Marc
Jones Jason
Mougenot Oliver
Auve Glenn A.
Donaldson Richard L.
Marshall, Jr. Robert D.
McClure C. Alan
Texas Instruments Incorporated
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