Host interface data receiver

Details Host interface data receiver Host interface data receiver

2007-05-22

2007-05-22

Vo, Don N. (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S360000, C375S371000

Reexamination Certificate

active

10608934

ABSTRACT:
A host interface includes transition detection circuitry, transition phase averaging circuitry, and bit stream sampling circuitry. The transition detection circuitry receives an incoming bit stream and a reference clock signal and detects transitions of the incoming bit stream with respect to the reference clock signal. The transition detection circuitry also determines relative phases of the transitions with respect to the reference clock signal. The transition phase averaging circuitry determines an average relative phase of the detected transitions with respect to the reference clock signal and also determines, based upon the average relative phase of the detected transitions with respect to the reference clock signal, a sampling phase with respect to the reference clock signal. The bit stream sampling circuitry samples the incoming bit stream at the sampling phase with respect to the reference clock signal to extract the bit values. The incoming bit stream may comply with the Universal Serial Bus 2.0 interface standard.

REFERENCES:
patent: 6263034 (2001-07-01), Kanack et al.
patent: 6556640 (2003-04-01), Baba
patent: 6760389 (2004-07-01), Mukherjee et al.
patent: 2003/0165207 (2003-09-01), Noguchi et al.

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