Patent
1995-07-26
1997-10-21
Harvey, Jack B.
395281, 395822, H01R 907, G06F 1340
Patent
active
056805551
ABSTRACT:
A host adapter, having at least two connectors which both belong to a single digital computer bus, includes a first terminator that is coupled to a first portion of the digital computer bus, and a second terminator that is coupled to a second, separate portion of the bus. Upon being enabled by a control signal, these terminators respectively terminate the first and second portions of the bus. The host adapter also includes termination control logic coupled to the first and second terminators, and to connectors for the bus. The termination control logic receives connection signals from the connectors which indicate connection or non-connection of a device to the first portion, or to the combined first and second portions of the bus. The termination control logic processes these connection sensing signals and transmits two independent control signals which appropriately enable or disable the first and second terminators. The host adapter may also include a third connector that also belongs to the bus, and from which the termination control logic also receives connection sensing signals. In addition to providing control signals for the terminators, the termination control logic also detects and indicates if devices are improperly connected to the bus.
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Bodo Martin J.
Rosenbloom Robert A.
Computer Performance Inc.
Harvey Jack B.
Pancholi Jigar
Scheiber Donald E.
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