Horizontally pipelined multiplier circuit

Details Horizontally pipelined multiplier circuit Horizontally pipelined multiplier circuit

1996-06-24

1998-06-02

Mai, Tan V.

Boots, shoes, and leggings

36476003, G06F 752

Patent

active

057611068

ABSTRACT:
A multiplier circuit (300, 400, 500, 600) uses a horizontal pipelining of the circuitry (301, 401, 501, 601) in order to reduce the number of gate-drain delays within the various data paths through the array (301, 401, 501, 601). Additionally, a combination of vertical and horizontal pipelining (550, 650) may also be implemented. The multiplier circuit (400, 600) may implement a modified Booth's algorithm. A horizontal pipeline latch (350, 450, 550, 650) operates to divide the array (301, 401, 501, 601) into two portions, where the first portion (360, 460, 560, 660) operates on the least significant bits of the resulting product, while the second portion (361, 461, 561, 661) operates on the most significant bits of that product.

REFERENCES:
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4825401 (1989-04-01), Ikumi

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