Horizontal scanning frequency multiplying circuit

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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Details

358158, 358147, H04N 506, H04N 704, H04N 504

Patent

active

045203946

ABSTRACT:
A horizontal scanning frequency multiplying circuit comprises a flip-flop supplied with an input horizontal synchronizing signal having a horizontal scanning frequency f.sub.H of a television signal, a phase-locked-loop (PLL) for producing a signal having a frequency Nf.sub.H (N is an integer over 1), a first counter supplied with an output signal of a voltage controlled oscillator within the PLL as a clock signal, for producing a counted output every time the clock signal is counted for a predetermined counting time T1 and supplying this counted output to the flip-flop to reset the flip-flop, a second counter supplied with the output signal of the voltage controlled oscillator as a clock signal, for counting this clock signal, a counted value setting circuit for producing a high-level output according to an output of the second counter when the second counter counts for a predetermined counting time T2, where T2>T1, and an OR-gate supplied with the input horizontal synchronizing signal and an output signal of the counted value setting circuit. The OR-gate supplies its output to the flip-flop to set the flip-flop and supplies its output to the second counter to reset the second counter.

REFERENCES:
patent: 4170026 (1979-10-01), Nagaaka et al.
patent: 4476490 (1984-10-01), Kaneko

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