Horizontal computer having register multiconnect for execution o

Details Horizontal computer having register multiconnect for execution o Horizontal computer having register multiconnect for execution o

1991-03-27

1993-07-06

Clark, David L.

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3642292, 3642613, 3642621, 364262, 364229, 364DIG1, 36493141, 364938, 3649468, 3649483, 3649462, 3649314, 364DIG2, G06F 9345, G06F 938

Patent

active

052261280

ABSTRACT:
A horizontal computer for execution of an instruction loop with a branch. The computer includes parallel processors, a multiconnect unit for storing operands for the processors, and instruction unit for specifying address offsets and operations to be performed by the processors, and an invariant address unit for combining the address offsets with a modifiable pointer to form source and destination addresses in the multiconnect unit. The instruction unit enables different ones of the processors both as a function of whether a branch instruction is to be executed and as a function of which iteration of the loop is being executed. The processors are enabled by processor control circuitry or by selectively providing instructions to the processors so that different operations are performed during different iterations.

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