Horizontal computer having register multiconnect for execution o

Details Horizontal computer having register multiconnect for execution o Horizontal computer having register multiconnect for execution o

1989-12-21

1992-01-21

Lee, Thomas C.

Boots, shoes, and leggings

3642283, 36422941, 3642621, 3642624, 36493101, 3649462, 3649427, 364DIG1, 364DIG2, G06F 900, G06F 1302, G06F 1516, G06F 1531

Patent

active

050832670

ABSTRACT:
A horizontal computer for executing a loop with recurrence. The computer features a horizontal architecture in which parallel processors repeatedly iterate a loop of instructions with recurrence, that is, where a result operand from one iteration is used as a source operand in a later iteration. Some of the processors provide result operands and some perform operations on source operands. A multiconnect register stores the operands at addressable locations. An instruction unit counts iterations and gives source and result address offsets relative to a modifiable pointer. An invariant address unit assigns a value to the modifiable pointer according to which iteration is being performed and combines the pointer with the offsets to provide source and destination addresses. An epilog counter stores a count of ending iterations in which progressively fewer instructions are executed in each succeeding iteration.

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