Television – Synchronization – Automatic phase or frequency control
Reexamination Certificate
2001-07-09
2004-05-04
Kostak, Victor R. (Department: 2614)
Television
Synchronization
Automatic phase or frequency control
C348S497000, C348S511000
Reexamination Certificate
active
06731344
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a horizontal automatic frequency control (AFC) circuit in a horizontal deflection circuit for driving a cathode ray tube (CRT) and particularly to a horizontal AFC circuit designed for reducing a horizontal distortion and horizontal jitter on a CRT screen.
BACKGROUND OF THE INVENTION
A horizontal automatic frequency control (AFC) circuit is a primary circuit for driving a cathode ray tube (CRT) display. A conventional horizontal AFC circuit will be described referring to the relevant drawings.
FIG. 5
is a block diagram of the conventional horizontal AFC circuit. A video signal processor
301
demodulates and converts a video signal
309
received into a YUV signal or an RGB signal. A synchronous separator
302
separates a horizontal sync signal and a vertical sync signal from the video signal
309
. An Hout signal circuit
304
is responsive to a horizontal (H) reference pulse
312
received from the synchronous separator
302
for generating a horizontal driving pulse
313
which drives a horizontal deflection driver
307
. A video signal driver
306
, upon receiving the YUV or RGB signal from the video signal processor
301
, generates a video signal for driving a CRT
308
. The horizontal deflection driver
307
, in responsive to the horizontal driving pulse
313
, controls horizontal deflection for the CRT
308
. Also, the horizontal deflection driver
307
generates a flyback pulse
311
. The H reference pulse
312
is synchronized with the video signal
309
.
FIG. 7
is a block diagram of the Hout circuit
304
. A counter
501
releases an H pulse
510
after a specific period of time from receiving the H reference pulse
312
. An HSAW circuit
502
generates a ramp-up sawtooth waveform signal at an H rate from the H pulse
510
. Another HSAW circuit
503
generates a ramp-up sawtooth waveform signal at an H rate from the H reference pulse
312
. A comparator
504
compares the sawtooth signal
511
from the HSAW circuit
502
with a DC voltage
514
from a low pass filter (LPF)
508
. When the sawtooth signal
511
is greater, the comparator
504
releases a high (H) level signal. Similarly to this, a comparator
505
compares the sawtooth signal
512
from the HSAW circuit
503
with the DC voltage
514
from the LPF
508
. And when the sawtooth signal
512
is greater, the comparator
505
releases an H level signal. A reset/set (RS) flip-flop
506
is reset when the comparator
504
outputs the H level, thus turning the horizontal driving pulse
313
to a low (L) level. When the comparator
505
outputs the H level, the flip-flop
506
turns the horizontal driving pulse
313
to the H level. A multiplier
507
multiplies the flyback pulse
311
by the H reference pulse
312
. An LPF
508
cuts off a high frequency component of an output
513
of the multiplier
507
.
An operation of the conventional horizontal AFC circuit having the foregoing arrangement will be explained.
FIG. 6
is a diagram illustrating the operation of the conventional horizontal AFC circuit. The synchronous separator
302
generates the H reference pulse
312
at horizontal rate from the video signal
309
. The Hout circuit
304
retards the H reference pulse
312
for a specific time to generate the H pulse
510
and releases the horizontal driving pulse
313
. The horizontal deflection driver
307
, upon receiving the horizontal driving pulse
313
, generates and releases the flyback pulse
311
. The delay of the flyback pulse
311
from the horizontal driving pulse
313
may be varied depending on a temperature and a load. This variation causes a horizontal position change on the CRT
308
.
For reducing the horizontal position change, the horizontal AFC circuit has the flyback pulse
311
synchronized in phase with the H reference pulse
312
. The horizontal AFC circuit incorporates a loop circuit including a multiplier
507
, an LPF
508
, comparators
504
and
505
, an RS flip-flop
506
, and a horizontal deflection driver
307
. In case that the flyback pulse
311
lags behind the H reference pulse
312
, the multiplier
513
outputs a signal where a lower portion from the center in the wave amplitude is greater than an upper portion. This declines the DC voltage
514
and positions the horizontal driving pulse
313
earlier than the H reference pulse
312
. As a result, a phase difference between the H reference pulse
312
and the flyback pulse
311
is eliminated, and thus the image on the CRT
308
does not move along the horizontal direction.
However, the conventional AFC circuit has the following disadvantage. When the Hout circuit
304
having an analog device is accompanied with a digital circuit in the video signal processor
301
and the synchronous separator
302
, the circuit
304
may be influenced by a clock signal in the digital circuit and a change of a power source voltage. Accordingly, a jitter in the horizontal driving pulse
313
is hardly attenuated.
SUMMARY OF THE INVENTION
A horizontal automatic frequency control (AFC) circuit reducing a horizontal distortion on a cathode ray tube (CRT) and hardly be affected by a digital noise, thus declining horizontal jitter.
The AFC circuit includes the following components:
(a) A synchronous separator for generating a horizontal (H) reference pulse from a video signal;
(b) An Hout signal generator for generating, from an output of the synchronous separator, a horizontal driving pulse which drives a horizontal deflection yoke of the CRT;
(c) A horizontal deflection driver for controlling horizontal deflection of the horizontal deflection yoke in responsive to the horizontal driving pulse;
(d) A line memory into which each line of the video signal is written along a write clock (WCK) enabled, and from which the video signal is read out with a read clock (RCK) which is synchronized with the flyback pulse which determines the starting point being started from the flyback pulse; and
(e) A read clock generator for generating the RCK from the flyback pulse.
REFERENCES:
patent: 4393413 (1983-07-01), Kaneko
patent: 4987491 (1991-01-01), Kaite et al.
patent: 6018408 (2000-01-01), Hong
patent: 6441860 (2002-08-01), Yamaguchi et al.
patent: 01132284 (1989-05-01), None
Shibutani Ryuichi
Taketani Nobuo
Kostak Victor R.
Matsushita Electric - Industrial Co., Ltd.
RatnerPrestia
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