Coating apparatus – Work holders – or handling devices
Reexamination Certificate
2002-06-13
2004-02-24
Edwards, Laura (Department: 1734)
Coating apparatus
Work holders, or handling devices
C118S728000, C269S903000, C156S345420
Reexamination Certificate
active
06695921
ABSTRACT:
TECHNICAL FIELD
The present invention broadly relates to semiconductor manufacturing equipment, and deals more particularly with a hoop support for supporting semiconductor wafer within a processing chamber.
BACKGROUND OF THE INVENTION
Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of the interconnect features is very important to the success of ULSI and to the continued efforts to increase circuit densities and quality on individual substrates and die. As circuit densities increase, the widths of vias, contacts, and other features, as well as the dielectric material between them, decrease to less than 250 nm, whereas the thicknesses of the dielectric layers remain substantially constant, with the result that the aspect ratios for the features decrease.
Copper and its alloys are being used with increased frequency to form lines and plugs in semiconductor processing, primarily because it exhibits lower resistivity than aluminum and significantly higher electro-migration of resistance as compared to aluminum. These characteristics are important for supporting higher current densities experienced at high levels of integration and increased device speed. Copper also has good thermal conductivity and is available in a highly pure state. Therefore, copper is becoming a choice metal for filling sub quarter micron high aspect ratio interconnect features on semiconductor substrates.
Metal electroplating is generally known and can be achieved using a variety of techniques. A typical method generally comprises physical vapor depositing a barrier layer on the feature surfaces, physical vapor depositing a conductive metal seed layer, preferably copper over the barrier layer, and then electroplating a conductive metal over the seed layer to fill the structure/feature. Finally, the deposited layers and the dielectric layers are planarized, such as by chemical mechanical polishing (CMP) to define a conductive interconnect feature.
One problem encountered in electroplating processes, sometimes referred to as electrochemical plating (ECP), is that the edge of the seed layer receives an excessive amount of deposition, typically referred to as an edge bead, during the electroplating process. The edge of the seed layer receives a higher current density than the remainder of the seed layer, resulting in a higher rate of deposition at the edge of the seed layer. The mechanical stress at the edge of the seed layer is also higher than the remaining of the seed layer, causing the deposition at the edge of the seed layer to pull up and away from the edge of the wafer.
Specialized equipment has been designed to remove the edge bead layer, which can be often combined with other processing equipment in a single station. For example, U.S. Pat. No. 6,267,853 issued Jul. 31, 2001, the entire contents of which are incorporated herein by reference, discloses a sophisticated electrochemical deposition system that includes automated stations for performing electrochemical deposition edge bead removal and spin/rinse/dry, rapid thermal annealing and seed layer repair. Edge bead removal is typically accomplished by spraying an etching solution on the edge of the wafer as the wafer is spun. The etching solution is dispensed at an angle to the wafer so that as the bead is removed, a bevel is formed on the wafer edge, and thus the process is sometimes referred to as “edge bevel removal” (EBR). EBR is carried out in an EBR chamber. The wafer is temporarily stored in the EBR chamber between processing operations using a hoop support having a plurality of pins that contact and support the wafer.
The pins directly contact the patterned side of the wafer. It has been found that a number of defects in the wafer often occur at the outer periphery of the wafer in the area of the pins. It has been determined that these defects are the result of impurities and contamination on the pins which are transferred to the surface of the wafer. These surface impurities are apparently the result of copper and other chemical impurities remaining on the pins after prior EBR processing of preceding wafers. It would therefore be desirable to provide supports that reduce the opportunity for copper and other chemical impurities and contaminants to be transferred to the surface of the wafer during EBR processing. The present invention is intended to provide this solution.
SUMMARY OF THE INVENTION
The present invention provides apparatus for supporting a semiconductor wafer between etching operations in which material is etched from the periphery of a wafer. The apparatus includes a hoop like structure, and a plurality of supports carried on the hoop for supporting a wafer thereon. Each of the supports is in the form of a pin having an edge that contacts and supports the wafer along the line of contact to provide adequate lateral support of the wafer while minimizing the contact area between the wafer and the supports. In a preferred form, the pins comprise a base and a pair of converging sides forming a triangular cross-section. The converging sides intersect to form the edge that contacts the wafer along a line. The pins are circumferentially spaced around the perimeter of the hoop and are arranged such that the line of contact with the wafer presents extends radially inward toward the center of the wafer. The angle of each of the sides defining the contact edge relative to the wafer is preferably between 60° and 80°. The sharp angle of the incidence of the sides of the pins, combined with a minimal contact area with the wafer, serve to reduce the opportunity for contaminants being carried on the pins that can be transferred to the wafer surface.
Accordingly, it is a primary object of the invention to provide a hoop for holding a semiconductor wafer in the processing chamber used to perform edge bevel removal operations.
It is a further operation of the intention to provide apparatus as described above which includes hoop supports that reduce the contact area between the hoop and the wafer.
A further object of the invention is to provide apparatus of the type mentioned which includes inclined surface features that reduce the opportunity for contaminants to adhere to the sides of the supports.
These, and further objects and advantages of the invention will be made clear or will become apparent during the course of the following description of the preferred embodiment of the invention.
REFERENCES:
patent: 6149727 (2000-11-01), Yoshioka et al.
patent: 6217663 (2001-04-01), Inokuchi et al.
patent: 6520191 (2003-02-01), Iwamoto et al.
Chen Chun-Chang
Cheng Hsi-Kuei
Huang Chin-Te
Lin Yu-Ku
Wang Ting-Chu
Edwards Laura
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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