Package making – Methods – Applying a partial cover
Reexamination Certificate
1999-05-10
2001-01-23
Johnson, Linda (Department: 3721)
Package making
Methods
Applying a partial cover
C053S419000, C053S447000
Reexamination Certificate
active
06176066
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Technical Field
This invention relates generally to packaging systems for semiconductor integrated circuits, and more particularly, to a novel, reusable, antistatic strapping method for securing stacks of trays containing arrays of semiconductor devices during testing operations, and which also allows for writing lot identification information directly onto the straps.
(2) Description of the Prior Art
In view of the trend for higher and higher packing densities for semiconductor integrated circuits or chips, electronic manufacturers have developed, in recent years, extremely miniaturized rectangular-shaped parts of the type having no terminal leads, such as pin grid array packages. Some of these types of pin grid array package structures are formed with solder balls on their bottom surface rather than with external terminal pins and are referred to as “ball grid arrays” (BGA) packages. Over the years, BGA packages of this type have become even smaller with extraordinary small outer dimensions and are somethimes referred to as “micro ball grid arrays,” or micro BGA packages. For example, a typical micro BGA package having forty-four solder balls on its bottom surface may have a length dimension of about 11 mm, a width dimension of about 6 mm and a thickness of about 2 mm.
During the manufacturing of semiconductor device packages, these packages are stored and transported to and from various types of processes or manufacturing equipment for carrying out different manufacturing or assembling steps. For example, the semiconductor device packages may be assembled, marked, tested, inspected and the like during which time the packages are handled and transported between the various manufacturing processes and/or machines. Further, after the processing steps have been completed, the semiconductor device packages are also packed and transported from a chip manufacturer's site to an assembly station at a customer's site where further assembly or testing operations are performed.
Heretofore, there is known in the prior art of a chip carrier tray having a plurality of separate compartments or pockets for accommodating a number of individual semiconductor device packages spaced apart from each other. Such a prior art chip carrier tray with a cover is illustrated in
FIG. 1
The chip carrier tray
11
and the cover
12
are both formed of a general square-shaped configuration.
FIG. 2
shows a cross-sectional view of the tray
11
which includes a plurality of separate compartments
15
each being capable of holding therein a single semiconductor device package
10
.
Conventionally, chip carrier trays are transported between manufacuring sites and processes in stacks of up to (and about) ten trays. The trays are banded together using antistatic strapping material
13
and are securely sealed by heat activation. The straps
13
must be cut and discarded at each manufacturing or processing stage. The restrapping process requires that many strapping machines be maintained in every corner of the test floor to minimize the transportation distance of unstrapped trays. In addition, the strapping material itself must be replaced at each step, a costly proposition for the manufacturer and/or end user.
SUMMARY OF THE INVENTION
The objective of this invention relates directly to an effective and cost-saving means of securing trays containing semiconductor device packages during transport between testing and other operations.
The main object of the invention is to allow for the transport of these trays efficiently and safely to minimize yield losses due to mechanical failure. This method ensures that trays can be secured immediately after testing, reducing Bend lead problems.
Another object of the invention is to utilize Velcro strapping which is recyclable to secure the trays rather than employ one-time-use strapping materials which must be cut and replaced at each testing or manufacturing stage.
Yet another object of this invention is to eliminate the need for heat activation of the strapping which has been the conventional approach to securing the trays. The reuseable Velco strapping material allows the trays to be secured without heat activation and without the heat activation machinery intrinsic to the process.
Yet another object of this invention is to save money by reducing the need for strapping machines on each test floor, as well as reduce costs of the strapping material needed. In the past, the strapping material had to be replaced at every manufacturing or testing step when the strap was cut to allow the semiconductor device packages to be removed. With this invention's use of Velcro as the strapping material, the straps can be opened without cutting and reclosed without heat activation and are, therefore, many times recyclable and reusable.
Still another object of this invention is to provide a neat and practical material handling on the test floor eliminating the need for multiple strapping machines and excessive strapping material use and to provide an easy means of identification of the tray lot. Lot identification (ID) can be written on the Velcro straps with a magic marker.
In accordance with the objectives of the invention, a method for safely securing a stack of trays containing semiconductor devices is achieved. An antistatic strapping apparatus for binding and securing a plurality of semiconductor device carrier trays, the apparatus including a strap member having opposed ends and a side defined as a top side spaced from a side defined as a bottom side and a major surface defined by the opposed ends and top and bottom sides. A loop portion of a hook and loop fastening combination constitutes the major surface area on the top side of the strap member. A piece of hook portion having the same width as the strap member of the hook and loop fastening combination secured to the top side at a first end of the strap member, the hook portion extending the length of said strap member by at least about 80 mm. A conductive thread is sewn in a multiplicity of lengthwise tracks on said second side of said major surface to prevent build-up of static electricity. A “L” shaped buckle having a first transverse slot formed therethrough and near the end of the longer leg, and a second transverse slot formed therethrough and near the end of the shorter leg. The second end of the strap member is inserted through first slot of the “L” shaped buckle and folded back to itself, the bottom surface contain conductive thread tracks facing out, is sewn to secure the second end to the “L” shaped buckle.
REFERENCES:
patent: 3191791 (1965-06-01), Jackson
patent: 4471872 (1984-09-01), Dedow
patent: 4730625 (1988-03-01), Fraser et al.
patent: 4868955 (1989-09-01), Magnant et al.
patent: 4876841 (1989-10-01), Jensen
patent: 5310076 (1994-05-01), Burton et al.
patent: 5400904 (1995-03-01), Maston et al.
Chang Francis
Ong Kester
Tan Chee Keong
Ackerman Stephen B.
Johnson Linda
Saile George O.
St Assembly Test Services Pte Ltd.
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