Hole grid array package and socket technology

Details Hole grid array package and socket technology Hole grid array package and socket technology

2001-11-01

2004-03-30

Cuneo, Kamand (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S261000, C174S050510, C361S760000, C361S785000, C361S787000, C361S801000, C257S727000, C257S698000

Reexamination Certificate

active

06713684

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to semiconductor packages and printed circuit board sockets. More particularly, the invention relates to a chip interface assembly having a hole grid array architecture.
2. Discussion
In the highly competitive computer industry, the trend toward higher processing speeds, reduced costs, and increased functionality is well documented. While this trend is desirable to the consumer, it presents significant challenges to motherboard designers as well as manufacturers. A particular area of concern relates to the socket that often provides interconnection between the semiconductor package and the motherboard or other printed circuit board (PCB). The socket enables an integrated circuit (IC) such as a computer processor to communicate with other components resident on the motherboard such as the main system memory, the basic input and output system (BIOS) and the motherboard chipset itself. While a number of sockets and slots have been developed over the years in order to facilitate this interconnection, the increasing speed of input/output (I/O) signaling in processor applications, the demand for lower costs, and the rapidly growing number of features have all presented a number of difficulties to industry participants.
A few particular difficulties relate to signaling throughput, hardware complexity, component clearance, and electrical losses. A conventional chip interface assembly includes a semiconductor package, a socket and an interconnection interface that passes I/O signals and reference signals between the package and the socket. While a number of interconnection interface architectures have evolved over the years, many of the above concerns remain. For example, one approach is to couple a male contact architecture, such as an array of pins, to the semiconductor package and provide the socket with a female contact architecture, such as a corresponding array of holes. Such a configuration is often referred to as a pin grid array (PGA). The above-described trend toward faster signaling, however, has dictated a sharp increase in the number of I/O pins required to achieve the desired signaling throughput. As a result, pin pitches have decreased correspondingly in order to satisfy space limitations. It has been determined, however, that there are manufacturing limitations on the number of pins that can be placed in a given area. Specifically, alignment tolerances and pin diameters are particular issues of concern. For example, as the pin diameter reduces, the strength of the pin also has a tendency to reduce. In fact, designers of conventional PGA packages have had considerable difficulty in reducing pin pitches below one millimeter as a result of the above concerns.
Furthermore, manufacturing capabilities have limited the ability to reduce the height of the pins on the semiconductor package beyond certain levels. As a result, the overall height of a PGA based chip interface assembly has a practical minimum value. Thus, the traditional PGA approach can have undesirable clearance consequences. In this regard, it should be noted that PGA packages typically require the socket to use a top cover, which moves the pins toward the contacts in the socket, and that this top cover increases the overall height of the chip interface assembly. In addition to clearance problems, the result can be electrical losses in the chip interface assembly such as an increase in self-inductance and/or loop inductance.
Other approaches to the chip interface assembly have involved coupling lands or balls to the socket interface surface of the semiconductor package and disposing a corresponding plurality of pads on the package interface surface of the socket. This approach is commonly referred to as the land grid array (LGA) or the ball grid array (BGA) approach. A compressive load is applied to the package and/or socket in order to force the lands or balls into electrical contact with the socket pads. While LGA and BGA packages allow for pin pitches to be reduced below one millimeter, the high uniform compressive load that must be maintained requires relatively complex mechanical hardware, which leads to increased costs. Thus, many of the conventional techniques fail to provide an ideal solution with respect to signaling throughput, cost, clearance and electrical losses.


REFERENCES:
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patent: 5973924 (1999-10-01), Gillespie, Jr.
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patent: 6243267 (2001-06-01), Chuang
patent: 410261758 (1998-09-01), None
patent: 2000031617 (2000-01-01), None

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