Hole geometry of a semiconductor package substrate

Details Hole geometry of a semiconductor package substrate Hole geometry of a semiconductor package substrate

1999-01-05

2001-02-20

Tran, Minh Loan (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S723000, C257S758000, C257S700000, C257S724000, C257S683000, C257S692000, C361S743000, C361S780000

Reexamination Certificate

active

06191472

ABSTRACT:

BACKGROUND OF THE INVENTION
1). Field of the Invention
The present invention relates generally to semiconductor packaging.
2). Discussion of Related Art
FIG. 1
of the accompanying drawings illustrates a prior art semiconductor package
10
which is in the form of a multichip module. The semiconductor package
10
includes a package substrate
12
and first and second integrated circuits,
14
and
16
respectively, mounted to the package substrate
12
by an array of bumps
18
or the like.
The package substrate
12
includes a number of insulative layers
20
with a layer of metal lines
22
, a sheet metal grounding layer
24
and a sheet metal power supply layer
26
sandwiched between the respective insulative layers
20
.
In order to test the semiconductor package
10
or in order to mount the integrated circuits
14
and
16
to the package substrate
12
it may be required to heat the semiconductor package
10
to a temperature sufficient for testing purposes or to a temperature sufficient to cause reflow of the material of the bumps
18
. The material of the insulative layers
20
may be a material such as a polyimide which creates a gas or gasses when being heated. Severe distortion and delamination of the layers of the package substrate
12
may occur if these gasses become trapped between the layers of the package substrate. In order to provide for outgassing of these gasses a number of openings
28
are formed in the grounding and power supply layers
24
and
26
. The gasses escape from between the layers of the package substrate
12
and collect within the openings
28
thereby preventing distortion or delamination of the layers of the package substrate
12
.
FIG. 2
is a plan view illustrating one of the metal layers
24
or
26
and the metal lines
22
A, B, C, D, E. The metal lines
22
A, B, C, D, E extend parallel to one another from one side to an opposing side of the package substrate
12
parallel with the metal layer
24
or
26
. The openings
28
are located within the substrate so that three of the metal lines (
22
A, B, and C) pass over the openings.
FIG. 3
is a view similar to
FIG. 2
wherein the metal lines
22
A, B, C, D, E are shown in phantom lines in a plane of the grounding layer
24
.
Referring again to
FIG. 1
, each integrated circuit
14
and
16
includes semiconductor electrical elements,
32
A, B . . . and
36
A, B . . . respectively, formed therein that may be transistors, capacitors, diodes or any other electrical elements. It is assumed, for purposes of discussion, that each of the electrical elements
32
A, B . . . in the first integrated circuit
14
is connected to a respective metal line
22
A, B, C, D, E and that each of the electrical elements
36
A, B . . . in the second integrated circuit
16
is also connected to a respective metal line
22
A, B, C, D, E and that each electrical element
32
A, B . . . in the first integrated circuit
14
switches a respective electrical element
36
A, B . . . in the second integrated circuit
16
by transmitting a signal through a respective metal line
22
A, B, C, D, E.
Each electrical element
32
A, B . . . and
36
A, B . . . is also connected to both the grounding layer
24
and to the power supply layer
26
. When the electrical elements
36
A, B . . . in the second integrated circuit
16
are switched, return currents pass through the grounding layer
24
back to the electrical elements
32
A, B . . . in the first integrated circuit
14
.
The switching signals from the electrical elements
32
A, B . . . in the first integrated circuit
14
through the metal lines
22
A, B, C, D, E to the electrical elements
36
A, B . . . in the second integrated circuit
16
are indicated by the arrows
42
in FIG.
2
.
The return currents from the electrical elements
36
A, B . . . in the second integrated circuit
16
to the electrical elements
32
A, B . . . in the first integrated circuit
14
are indicated by the arrows
46
in FIG.
3
.
At high frequencies the return currents
46
tend to follow the paths of least inductance which tend to be localized below the respective metal lines
22
A, B, C, D, E. However, since the metal lines
22
A, B and C pass over the openings
28
, the return currents
46
corresponding to the metal lines
22
A, B, and C are diverted around the openings
28
.
Due to diversion of the return currents
46
a measure of interference or “crosstalk noise” occurs between some of the return currents
46
(see for example the return currents
46
corresponding to the metal lines
22
B, C and D).
Crosstalk noise between the return current
46
may affect the respective switching signals
42
relative to one another. High levels of crosstalk noise may even result in the switching signals
42
being so dramatically affected that incorrect switching of the electrical elements
36
A, B . . . in the second integrated circuit
16
results, and is thus undesirable.
It can also be seen from
FIG. 3
that the return signals
46
which are diverted around the openings
28
follow a longer path. By following a longer path, some of the return signals
46
may be delayed relative to one another, which, in turn, may result in delay in switching of the switching signals
42
relative to one another. Delay in the switching signals
42
relatively to one another results in “clock skew” in the switching of the electrical elements
36
A, B . . . in the second integrated circuit
16
. For example, should two or more of the electrical elements
32
A, B . . . in the first integrated circuit
14
be clocked to simultaneously switch and therefore simultaneously transmit the switching signals
42
, a delay would occur in switching one of the electrical elements
36
A, B . . . relatively to switching of another of the electrical elements
36
A, B . . . in the second integrated circuit.
A longer return signal will generally result in an increase in inductance (L). Inductance (L) can therefore be used as a measure for comparing delay of the return signals.
Furthermore, capacitances between the metal lines
22
A, B, C, D, E and the grounding and power supply layers
124
and
126
also affect delay of the return signals. A decrease in capacitance (C) of a respective metal line
22
A, B, C, D, E will generally result in less delay of the return signals.
Characteristic impedance can therefore be expressed by the formula:
Characteristic Impedance={square root over (L
s
+L /C
s
+L )} where
L
s
is self inductance; and
C
s
is self capacitance.
A higher characteristic impedance will generally result in more delay.
EXAMPLE 1
FIG. 4
of the accompanying drawings illustrates schematically three of the metal lines
22
A, B, and C and the grounding and power supply layers
24
and
26
in cross-section on
4
—
4
in FIG.
1
.
The metal lines
22
A, B, and C are spaced from the grounding layer
24
by a distance D
1
of about 74 &mgr;m and from the power supply layer
26
by a distance D
2
of about 30 &mgr;m. Each metal line
22
A, B and C is about 37 &mgr;m thick and the grounding and power supply layers
24
and
26
are each about 22 &mgr;m thick. The pitch P from metal line to metal line is about 110 &mgr;m. Each metal line is about 2 cm long and is spaced from an adjacent metal line by about 74 &mgr;m.
At 1 GHz the following characteristic impedances are calculated for the respective metal lines:
Metal line 22A
Metal line 22B
Metal line 22C
53.8
61.8
55.0
It can therefore be seen that, for the given set of parameters, the characteristic impedances vary by a relatively large 36%. Such a relatively large variation in characteristic impedances results in a relatively large delay between switching signals of the metal lines
22
A, B and C.
In an analysis of delay performance, the voltages at ends of the outer metal lines
22
A and
22
C are switched from high to low (attacker input). The central metal line
22
B is held low. An output voltage is measured at an opposing end of the metal lines
22
A and
22
C to obtain an indication of delay.
FIG. 9
is a graph illustrating the attacker input voltage and

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