Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-12-30
2004-07-20
Tran, M. (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S203000
Reexamination Certificate
active
06765842
ABSTRACT:
TECHNICAL FIELD
A hole driver of a row address path for a semiconductor memory device is disclosed.
DESCRIPTION OF RELATED ART
Generally, a semiconductor memory device has a row address path and a column address path. Blocks configuring the row address path and signals are represented as a symbol ‘X’ and blocks configuring the column address path and signals are represented as a symbol ‘Y’.
The row address path includes a row control block, a row address strobe (RAS) signal generating block, an address latch block and a X-hole block.
FIG. 1
is a block diagram illustrating the row address path. The semiconductor memory device, i.e., specially, DRAM has a plurality of banks. Two banks BANK
0
and BANK
1
are shown in FIG.
1
. Each bank has a plurality of sub blocks including a cell array. A sense amplifier S/A is disposed between each sub block. Each bank further has an X-hole including a row decoder X-DEC, a sense amplifier control unit, a wordline (W/L) enable control unit and an X-DEC control unit.
The semiconductor memory device has a hole driver or driver circuit for driving the X-hole, the hole driver including a bank control unit and a block address pre-decoder BAX. The bank control unit drives the sense amplifier control unit S/A and the W/L enable unit in the corresponding X-hole by receiving an output of a row address strobe signal generating block (not shown) and the block address pre-decoder drives the X-decoder control unit in corresponding X-hole by pre-decoding an address outputted from an address latch block (not shown) under control of the bank control unit.
In addition, when the output of the block address pre-decoder BAX is directly applied to the row decoder X-DEC, since drivability of the output thereof decreases due to a high load, a local address pre-decoder LAX is further included in the X-DEC control unit in the X-hole.
FIG. 2
is a block diagram illustrating the conventional hole driver in FIG.
1
.
As shown, the hole driver includes a first bank control unit
22
, a second bank control unit
24
and a block address pre-decoder
20
. The first bank control unit
22
receives a row active pulse signal ractzp
13
x and a row precharge pulse signal rpcgzp
13
x outputted from the row address strobe signal generating block (not shown) and generates bank active pulse signals bxatvp
16
and bxatvp
22
, bank precharge pulse signals bxpcgzp
19
and bxpcgzp
21
, a wordline clear signal wlcz and a wordline enable control signal bsenz. The second bank control unit
24
receives the bank active pulse signal bxatvp
22
, the bank precharge pulse signal bxpcgzp
21
and the wordline clear signal wlcz and generates a sense amplifier operation starting signal bsg. The block address pre-decoder
20
, which includes a plurality of sub blocks BAX
01
, BAX
23
, BAX
45
, BAX
678
, BAX
9
A and BAXBC, pre-decodes the row address signals at-row<
0
:
12
> outputted from the row address latch block (not shown) in response to the bank active pulse signal bxatvp
16
and the bank precharge pulse signal bxpcgzp
19
.
FIG. 3
is a circuit diagram illustrating the second bank control unit
24
in FIG.
2
.
As shown, the second bank control unit
24
includes a first driver
30
, a first inverter latch
31
, a first delay
32
, a second driver
33
, a second inverter latch
34
and a pulse generator
35
. The first driver
30
includes a PMOS transistor M
1
and an NMOS transistor M
2
, whose gates receives the bank precharge pulse signal bxpcgzp
21
and the bank active pulse signal, respectively. The first inverter latch
31
includes two inverters INV
1
and INV
2
connected to an output of the first driver
30
and the first delay
32
delays an output of the first inverter latch
31
for a predetermined time. The second driver
33
includes an NMOS transistor M
7
whose gate receives the wordline clear signal wlcz, an NMOS transistor M
8
whose gate receives an output signal of the first delay
32
and a PMOS transistor whose gate receives the wordline clear signal wlcz, wherein the transistors M
9
, M
8
and M
7
are connected in series between a power supply voltage xvdd and a ground voltage. The second inverter latch
34
includes an inverter INV
5
connected to an output terminal of the second driver
33
and a PMOS transistor M
10
for supplying a power supply voltage to the output terminal of the second driver
33
by receiving an output of the inverter INV
5
to a gate thereof. The pulse generator
35
generates the sense amplifier operation starting signal bsg by receiving an output signal of the second inverter latch
34
.
The first delay
32
includes a plurality of unit delays
36
. The unit delay
36
includes a CMOS inverter INV
3
having a resistance R connected a pull-down terminal thereof, MOS transistors M
3
, M
4
, M
5
and M
6
and switches S
1
, S
2
, S
3
and S
4
configuring a capacitor load and an inverter INV
4
.
The pulse generator
35
includes a second delay
37
for delaying an output signal of the second inverter latch
34
for a predetermined time, a NOR gate NOR
1
receiving the output signal from the second inverter latch
34
and an output signal of the second delay
37
, inverters INV
6
, INV
7
and INV
8
for buffering an output signal from the NOR gate NOR
1
and outputting the sense amplifier operation starting signal bsg. The second delay
37
includes a plurality of unit delays, which are the same with those of the first delay
32
.
The output signal of the second bank control unit
24
, that is to say, the sense amplifier operation starting signal bsg is a flag signal for notifying when a driving operation of the sense amplifier is carried out after corresponding wordlines are completely enabled by inputting all row address signals to the X-hole and charge sharing operation for a bitline and a memory cell is completed.
FIG. 4
is a circuit diagram illustrating a first sub block BAX
01
in the block address predecoder
20
(see FIG.
2
).
As shown, the first sub block BAX
01
receives the row address signal at_row<
01
> and outputs predecoded row address signals Bax
01
<
0
:
3
>. A circuit for generating the BAX
01
<
0
> signal includes a driver
41
, a latch
42
and a buffer
43
. The driver
41
consists of a PMOS transistor M
11
and NMOS transistors M
12
, M
13
and M
14
connected in series between a external voltage Vext and a ground voltage. The bank precharge pulse signal bxpcgzp
19
is applied to a gate of the PMOS transistor M
11
. The bank active pulse signal bxatvp
16
, an address signal atz<
0
> and an address signal atz<
1
> are applied to gates of the NMOS transistors M
12
, M
13
and M
14
, respectively. The address signal atz<
0
> is an inverted row address signal at_row<
0
> and the address signal atz<
1
> is an inverted row address signal at_row<
1
>. Also, an address signal at<
0
> is an inverted address signal atz<
0
> and an address signal at<
1
>is an inverted address signal atz<
1
> shown in FIG.
4
.
The latch
42
consists of two inverters INV
9
and INV
10
and an output of the driver
41
, which is a junction of the PMOS transistor M
11
and the NMOS transistor M
12
, is connected to an input of the inverter INV
10
. The buffer
43
includes a plurality of inverters INV
11
and INV
12
for outputting the Bax
01
signal.
Circuits for generating the predecoded Bax
01
<
1
>, Bax
01
<
2
> and Bax
01
<
3
>signals are similar to the circuit for generating the Bax<
0
> signal. The differences are that the address signals at<
0
> and atz<
1
> are applied to generate the Bax
01
<
1
> signal instead of the address signals atz<
0
> and atz<
1
> and the address signals atz<
0
> and at<
1
> are applied to generate the Bax
01
<
2
> signal. Also, the address signals at<
0
>and at<
1
> are applied to generate the Bax
01
<
3
> signal.
If a row active command is applied from an external circuit, a row address strobe (RAS) signal and an address signal are inputted
Hynix / Semiconductor Inc.
Tran M.
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