Hold-up circuit with safety discharge for preventing shut-down b

Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...

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307 66, 361 92, G05F 140, H02J 700

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active

058282076

ABSTRACT:
A storage capacitor of a hold-up circuit is connected by a resistor to the urrent conducting bus supplying operating voltage to computer hardware from a power source. The capacitor is thereby charged to the operating voltage level in order to subsequently maintain computer operation by discharge through a diode during power interruption of a relatively long duration determined by the capacitor charge and a predetermined drop in voltage applied to the computer load causing its shutdown. Detection of such drop in voltage is operative through an opto-isolator to safely discharge the capacitor by relay controlled grounding thereof.

REFERENCES:
patent: 4709320 (1987-11-01), Konopka
patent: 4771356 (1988-09-01), Hastings
patent: 4819116 (1989-04-01), Piteo
patent: 5140511 (1992-08-01), Lee et al.
patent: 5153497 (1992-10-01), Eiden
patent: 5161097 (1992-11-01), Ikeda

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