Hold time margin increased semiconductor device and access time

Details Hold time margin increased semiconductor device and access time Hold time margin increased semiconductor device and access time

1998-03-19

2000-06-27

Ton, My-Trang Nu

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327161, H03L 706

Patent

active

060811420

ABSTRACT:
A load adjusting circuit 36 adjusts the load value L=L2 of a dummy load circuit 31x corresponding to the outputs of a frequency determining circuit 37 and an interface determining circuit 35 as L2=L1-.DELTA.L holding, where L=L1 is a proper value in the case that the access time does not depend on the frequency of the data DQ and .DELTA.L corresponds to a half of the maximum value tlc of the deviation of the access time that varies corresponding to the frequency of the data DQ. A DLL circuit 40 delays a internal clock iCLK by a time .delta.tx so that a difference between phases of the clock iCLK and a dummy internal clock d.sub.-- iCLK becomes a predetermined value. The delay time .delta.tx is equal to a value determined in such a way that .delta.tx=67 tx0 is determined with activating the DLL circuit 40, tlc is determined and .delta.tx is finally determined as .delta.tx=.delta.tx0+ tlc/2 or .delta.tx=.delta.tx0-tlc/2 due to the condition of data frequency at determining .delta.tx0.

REFERENCES:
patent: 4922141 (1990-05-01), Lofgren et al.
patent: 5087829 (1992-02-01), Isgibashi et al.
patent: 5486783 (1996-01-01), Baumert et al.
patent: 5670903 (1997-09-01), Mizuno
patent: 5740123 (1998-04-01), Uchida
patent: 5852380 (1998-12-01), Yamauchi

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