Hit predictive cache memory

Details Hit predictive cache memory Hit predictive cache memory

1988-03-15

1990-03-27

Heckler, Thomas M.

Boots, shoes, and leggings

36424341, 36424611, 364253, G06F 1212

Patent

active

049126261

ABSTRACT:
A cache memory when receiving an operand read request and the operand address from a central processing unit responds with a signal indicative of an operand being available in the cache memory before having checked if such operand is effectively in the cache or if in a previous operand request, the effective operand presence in the cache had occurred or started a memory read operation before having checked if such operand is effectively not present in the cache or if in a previous operand request, the effective absence of the operand from the cache has occurred. The decision among the two alternatives is determined by state logic which stores the previously occurred HIT condition denoting the requested operand presence in the cache or MISS condition denoting the requested operand absence from the cache memory. The states of these conditions are updated during the course of a current read operation if a predicted HIT condition is followed by an effective MISS condition or if a predicted MISS condition is followed by an effective HIT condition.

REFERENCES:
patent: 4363095 (1982-12-01), Woods et al.
patent: 4445177 (1984-04-01), Bratt et al.
patent: 4458310 (1984-07-01), Chang
patent: 4603380 (1986-07-01), Easton et al.

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