History buffer system

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395410, 395800, 364DIG2, 3649236, 3649262, 36493111, 36493152, G06F 938

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active

055817750

ABSTRACT:
A history buffer system (12) for allowing the recovery of executed instructions comprises main history buffer (14) for storing addresses of issued instructions and at least one subsidiary history buffer (16, 22) associated with a predetermined type of data, such as fixed or floating point data. The subsidiary history buffer (16, 22) has a plurality of entries (Y, Z), each entry for storing a pointer to a register (18, 26) and the data stored in the register. The main history buffer (14) is arranged to store control data (fxtag, fptag) which associates the entries in a subsidiary history buffer with the appropriate issued instructions of the same data type stored in the main history buffer. The main history buffer (14) may comprise a storage entry for each issued instruction, each storage entry having a field for storing the address of an issued instruction, and at least one tag field (fxtag, fptag) corresponding to the at least one subsidiary history buffer (16, 22) for storing the control data.

REFERENCES:
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patent: 5450560 (1995-09-01), Bridges et al.
Patt et al. "Critical Issues Regarding HPS, a High Performance Microarchitecture", ACM 1985.
Smith et al "Implementing Precise Interrupts in Pipelined Processors" IEEE 1988.
Wang et al. "Area and Performance Comparison of Pipelined RISC Processors Implementing Different Precise Interrupt Methods" Jul. 1993, IEEE.
Hwu et al. "Design Choices for HPS in Microprocessor Chip", 1987.
Wang et al. "Implementing Precise Interruptions in Pipelined RISC Processors" IEEE Aug. 1995.
James E. Smith et al., IEEE Transactions on Computers, "Implementing Precise Interrupts in Pipelined Processors", May 1988, No. 5, pp. 562-573.

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