Highspeed parallel adder with clocked switching circuits

Details Highspeed parallel adder with clocked switching circuits Highspeed parallel adder with clocked switching circuits

1984-11-27

1987-10-20

Malzahn, David H.

Boots, shoes, and leggings

364786, G06F 750

Patent

active

047018771

ABSTRACT:
In a parallel adder circuit, first and second full adders each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal are alternately connected such that the carry output terminal of the preceding full adder is directly connected to the carry input terminal of the succeeding full adder. In order to shorten the carry propagation delay time, the first full adder is arranged to receive an inverted carry signal (FALSE) from the preceding stage and to provide a carry signal (TRUE) to the succeeding stage, while the second full adder is arranged to receive a carry signal (TRUE) from the preceding stage and to provide an inverted carry signal (FALSE) to the succeeding stage.

REFERENCES:
patent: 4052604 (1977-10-01), Maitland et al.
patent: 4523292 (1985-06-01), Armer et al.
patent: 4601007 (1986-07-01), Uya et al.
Japanese Patent Disclosure (KOKAI) Nos. 56-147235, and 56-147236, Nov. 16, 1981.

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