Highspeed extendable bus architecture

Details Highspeed extendable bus architecture Highspeed extendable bus architecture

1999-01-04

2002-09-03

Corrielus, Jean (Department: 2631)

Pulse or digital communications

Systems using alternating or pulsating current

Plural channels for transmission of a single pulse train

C375S288000, C341S100000

Reexamination Certificate

active

06445744

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to transmission systems, and more particularly relates to high speed bus architectures.
2. Related Art
While new microprocessors continue to process data at ever increasing speeds, the rate at which data can be delivered to the microprocessor, i.e., the bus speed, has failed to keep pace. Thus, an important challenge for system designers is how to increase bus speeds so that high speed microprocessors are not bogged down waiting for data. In particular, new techniques are sought that can increase the rate of data flow from memory devices, such as dynamic random access memory (DRAM) to the microprocessor in order to allow high speed microprocessors to operate at their designed speeds.
Unfortunately, several critical factors exist that relate to the speed at which a bus can deliver data. The most important relates to the fact that faster bus speeds are more susceptible to problems associated with noise. Furthermore, as bus signal levels decrease, noise becomes more and more problematic. Thus, higher voltage bus signals are preferable in eliminating noise. Unfortunately, it generally takes a longer amount of time to switch a high voltage signal as compared with a low voltage signal because a larger current drive is required.
A final consideration relates to power, which is particularly important for mobile systems, such as laptops and portable phones. High speed bus systems generally require a higher amount of power, which can be counter to what is required for a particular application. High speed busses tend to draw a large amount of power because present bus architectures require transmission line techniques with resistive termination on at least one end of each transmission line, or more frequently, on both ends. By requiring terminating resistors on a bus, significant power dissipation is introduced into the system. Thus, attempting to drive full CMOS logic levels over resistively terminated transmission lines leads to large and cumbersomely slow drivers with high power dissipation. While smaller, faster drivers with less skew are available, they produce less than full CMOS logic levels when driving typical terminated transmission line impedances. While smaller logic levels are possible, they tend to be more susceptible to ambient noise unless protected by some special technique.
As is evident, competing factors exist that make it difficult to provide a high speed, low power, noise free bus architecture. Although various attempts have been made to overcome these issues, no inexpensive solutions presently exist.
SUMMARY OF THE INVENTION
The present invention overcomes the above-mentioned problems in the related art by providing a bus system that can transmit n-bit packets of binary data, the bus system comprising: an encoder system on the transmission end for converting each n-bit packet of data into a unique set of m signals, wherein the m signals have a net current sum of zero; m transmission lines for transmitting the m signals; and a decoder on the receiving end for receiving the m signals and converting them back to the original n-bit packet of data. In order to provide a net current sum of zero, the encoder comprises drivers for providing signals of differing polarities.
By providing a set of signals with a zero sum net current, the transmission lines no longer require an external reference (e.g., ground) for a return signal. Rather, the circuit is completed within the transmission lines themselves. Because the invention eliminates the need for an external reference, noise problems associated with voltage differences between the external reference and the transmission line are eliminated. Thus, relatively low voltage signals may be utilized, for example, only fifty or a hundred millivolts.
The invention further features differential sensing on the receiving end in order to convert the mixed polarity m signals back into binary data. In addition, the m signal lines can be utilized to accurately transmit a relativistic clock as part of the data and therefore avoid most signal-to-clock skew problems.
Finally, because of the simplicity of the design, the system can be easily replicated to handle multiple n-bit packets therefore providing an extendable system having a virtually unlimited bus width.
The foregoing and other objects, features and advantages of the invention will be more apparent in the following and more particular description of the embodiments of the invention as illustrated in the accompanying drawings.


REFERENCES:
patent: 4020282 (1977-04-01), Halpern
patent: 4293949 (1981-10-01), Philippides
patent: 4608702 (1986-08-01), Hirzel et al.
patent: 5034967 (1991-07-01), Cox et al.
patent: 5046072 (1991-09-01), Shimizu et al.
patent: 5525983 (1996-06-01), Patel et al.
patent: 5612958 (1997-03-01), Sannino
patent: 5640605 (1997-06-01), Johnson et al.

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