Oscillators – Phase shift type
Reexamination Certificate
2002-01-18
2003-10-28
Choe, Henry (Department: 2817)
Oscillators
Phase shift type
C331S111000, C331S03600C, C331S137000
Reexamination Certificate
active
06639479
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates to time reference sources and, more particularly, integrated time references within a device for use either as a clock reference or calibration master in a master-slave continuous-time filter system.
2. Related Art
Integrated time references are essential in integrated devices and are used for many purposes including synchronization of internal operations, synchronization with buses and external networks among other applications. For example, for a device that communicates over an external synchronized bus, it is important that the device has an internal time reference that it can use to detect and respond to the signals on the bus. Generally, synchronized buses require that all operations happen at specified instants in time. Thus, a device must not only be able to read the synchronized signals being received on the bus, but must also be able to transmit at specified instants in a synchronized manner.
Crystal oscillators have long been used to provide very accurate time keeping functions as result of their steady and predictable response to physical or electrical stimuli. Integrated circuits, however, by their very nature, cannot incorporate an internal crystal oscillator. Accordingly, integrated circuit oscillators are often designed using integrated resistors and capacitors to achieve an RC time constant based oscillation. One problem with this approach, however, is that RC time constants vary significantly according to the tolerance of the resistors and capacitors configured to provide the RC time constants. It is, therefore, difficult to design RC time constant circuits for which their operation is predictable and reliable.
In cases where integrated components are required to achieve accuracy, for example, to enable predictable filter response to be achieved, a more stable external device may be used as a reference. There are times, however, where it is disadvantageous to have a device or integrated circuit be coupled to receive precise frequency signals from an accurate external source.
Accurate internal time keeping is needed, for example, by analog-to-digital converter (ADC) circuits. ADC's are complex analog-to-digital converters that are often used to digitize analog wave forms, for example, voice wave forms, as a part of converting a voice signal to a digital signal that may be manipulated, stored or transmitted over a wireless medium.
The conversion of the voice signal from analog to digital will be most accurate and most reproducible if the sampling occurs at precise and constant measures of time. Moreover, internal synchronized buses, for another example, also require accurate time keeping so that a receiver can properly determine when to latch a data signal. A transmitter must be able to accurately drive a signal on a synchronized bus. Thus, for these and many other reasons, a need exists not only for internal time sources that may be used as a reference signal, but also for accuracy.
SUMMARY OF THE INVENTION
A reference voltage is used to generate a current that is proportional to the conductance of a resistor, or transconductor element, where it is then conducted into a circuit in which the current is integrated onto a discharged capacitor. The voltage across the capacitor is compared with the reference voltage by a comparator wherein a reset is triggered whenever the voltage integrated onto the capacitor exceeds the reference voltage. The reset signal is fed back into a switch that resets the integration capacitor and repeats the integration on the same capacitor or in a closely matched second capacitor. Accordingly, the resistor capacitor pair forms an RC time constant that, coupled with the comparator, serves to create a stable oscillator. In order to obtain a stable time reference with the desired oscillation frequency, a capacitor array is utilized not to provide a desired capacitance, but rather to provide an adjustable time constant to create an oscillation of the desired frequency.
A method of the present invention includes a process for adjusting the RC time constant to obtain a time reference that matches a master reference. More specifically, the method includes, in a processing unit, generating control signals to cause a mid-level capacitance value to be set. Thereafter, the capacitance values are adjusted either upwards or downwards according to the difference in the frequency between the clock driven by the RC time constant and the master source.
In one embodiment of the present invention, an RC oscillator has its clock values driven into a counter that resets the counter value after a specified number of clock cycles. For example, in one embodiment of the invention, the counter value is reset every 1,000 clock cycles. Each time the counter value is reset, it also sends a reset signal to a master counter that receives clock signals from a master clock to which the RC oscillator is being calibrated. When the master counter receives the reset signal, it generates an external count value that is used by the calibration logic to adjust the frequency of the RC oscillator.
For example, since the RC oscillator's counter is reset after 1,000 clock cycles, its frequency is too high if the master counter value is less than 1,000 clock cycles. Conversely, if the master counter has a higher value than 1,000, the RC oscillator clock frequency is too low. Based upon that information, a calibration logic circuit adjusts the capacitance (and, therefore, RC time constant within the RC oscillator) to increase or decrease the oscillation frequency as is necessary. More specifically, the calibration logic generates control commands to add or delete switched capacitors to a capacitor array that creates the RC time constant.
The specific logic that is implemented by the calibration logic for adjusting the capacitance may vary from system to system. In the present system, however, the calibration logic is optimized to reduce the number of iterations that is required to achieve an RC oscillator frequency that most closely matches the frequency of the master clock. Accordingly, the calibration logic examines the remaining amount of capacitance that may be changed and adjusts that capacitance value by a value that approximately equals half of that capacitance amount that may be adjusted.
Other aspects of the present invention will become apparent with further reference to the drawings and specification, which follow.
REFERENCES:
patent: 4200863 (1980-04-01), Hodges et al.
patent: 5581252 (1996-12-01), Thomas
patent: 5675340 (1997-10-01), Hester et al.
Gloerstad Terje
Kappes Mike
Broadcom Corporation
Choe Henry
Garlick Bruce
Harrison James
Markison Tim
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