Highly stable high-voltage output buffer using CMOS technology

Details Highly stable high-voltage output buffer using CMOS technology Highly stable high-voltage output buffer using CMOS technology

1990-10-22

1992-12-08

Howell, Janice A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307264, 307570, 307270, 330264, H03K 17087

Patent

active

051700786

ABSTRACT:
A highly stable high-voltage output buffer is provided which may be manufactured using standard CMOS technology. As part of the invention, the effects of voltage drift at one or more of the nodes formed between series connected P or N-channel MOSFET devices are generally reduced or eliminated. The present invention includes compensation circuitry which reduces the effects of parasitic coupling within the MOSFET devices, and which serves to compensate for any voltage drift which may occur at the nodes between series connected devices. In addition, the present invention provides a method and apparatus for increasing the current sourcing capability of a CMOS high-voltage output buffer, even under low supply V.sub.vf conditions, without necessarily increasing the size of the output device. Furthermore, the present invention provides a method and apparatus for reducing the effects of coupling along a shared bias line between a plurality of high-voltage output buffers in accordance with the present invention.

REFERENCES:
patent: 4490629 (1984-12-01), Barlow et al.
patent: 4622482 (1986-11-01), Ganger
patent: 4638187 (1987-01-01), Boler et al.
patent: 4837457 (1989-06-01), Bergstrom et al.
patent: 4988888 (1991-01-01), Hirose et al.
patent: 5057789 (1991-10-01), Nagaraj

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