Highly scaleable dynamic ram cell with self-signal amplification

Details Highly scaleable dynamic ram cell with self-signal amplification Highly scaleable dynamic ram cell with self-signal amplification

1981-07-13

1983-11-22

Stellar, George G.

Static information storage and retrieval

Floating gate

Particular biasing

365168, 365184, 365187, 365210, 357 22, 427 85, 427 86, 427 88, 427 96, 357 23, G11C 1140, H01L 2980, H01L 2978, B05D 512

Patent

active

044173253

ABSTRACT:
A memory cell comprises a substrate of a first conductivity type (preferably N type) in which is formed a first region of opposite conductivity type. Second, third and fourth regions of first conductivity type are then formed in the first region, said second and third regions being separated by a first portion of the first region and said third and fourth regions being separated by a second portion of the first region. A fifth region of first conductivity type is then formed in the second portion of the first region and a first electrode is attached to the fifth region. This electrode is electrically isolated from the second, third and fourth regions and extends on insulation over the first portion of said first region to said second region and also extends over said third region and a part of the second portion of said first region. This electrode is covered by insulation. A word line is then formed over the insulation on the first electrode so as to overlie the first electrode and together with the first electrode forms a dual electrode. The dual electrode structure forms a read transistor with channel length measured by the extent of the first portion between said second region and said third region and a write transistor with channel length measured by the separation between said third region and said fifth region, and a storage junction formed between said fifth region and said first region. By varying the voltage on the third region during the driving of the word line to either a positive or negative voltage, the charge on the first electrode is varied thereby varying the threshold voltage of the read transistor as seen by the word line. A plurality of memory cells such as described can be used to form an array and by varying either the capacitive coupling between the word line or third region and the first electrode in a selected memory cell or, alternatively, by varying the voltage applied to the third region during the writing on said first electrode of stored charge, this particular cell can be used as a reference cell during the read operation.

REFERENCES:
IEEE Trans. Ed., vol. 26, #6, Jun. 1979, Chatterjee et al., "A Survey of High Density Dynamic Ram Cell Concepts".
IEDM Abstracts 1980, (IEEE Publication), "A New Dynamic Ram Cell for VLSI Memories", Terada et al.

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