Highly-scalable hardware-based traffic management within a...

Multiplex communications – Data flow congestion prevention or control – Control of data admission to the network

Reexamination Certificate

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C370S395400

Reexamination Certificate

active

07742411

ABSTRACT:
A technique for managing traffic within a network processor integrated circuit (IC) involves establishing multiple queue groups, associating a different hardware counter with each queue group, and then using the hardware counters to support rate shaping and scheduling of all of the queues in the queue groups. For example, 512 queue groups of thirty-two queues each queue group are established for a total of 16,384 (16 k) different queues and a different hardware counter is associated with each queue group for a total of 512 hardware counters. The group-specific hardware counters are used to implement hardware-based rate shaping and scheduling of all 16 k queues in a resource efficient manner that supports high throughput, e.g., on the order of 40 Gbps.

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Papaefstathiou, Orphanoudakis, Kornaros, Kachris, Mavroidis, Nikologiannis; “Queue Management in Network Processors”; Proceedings of the Design, Automation and Test in Europe Conference and Exhibition; 2005; 6 pgs.; IEEE Computer Society.
Maki, Shimonishi, Murase, Murata, Miyahara; “Hierarchically Aggregated Fair Queueing (HAFQ) for Per-flow Fair Bandwidth Allocation in High Speed Networks”; Graduate School of Information Science and Technology, Osaka University; 6 pgs.; Networking Research Labs, NEC Corporation.
Kramer, Banerjee, Singhal, Mukherjee, Dixit, Ye; “Fair Queueing with Service Envelopes (FQSE): A Cousin-Fair Hierarchical Scheduler for Subscriber Access Networks”; IEEE Journal on Selected Areas in Communications; Oct. 2004; 1 page; vol. 22, No. 8.

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