Highly scalable dynamic RAM cell with self-signal amplification

Details Highly scalable dynamic RAM cell with self-signal amplification Highly scalable dynamic RAM cell with self-signal amplification

1982-03-08

1984-05-15

Stellar, George G.

Static information storage and retrieval

Floating gate

Particular biasing

357 23, 365168, 365182, 365184, 365186, G11C 1140, G11C 1156

Patent

active

044484003

ABSTRACT:
A dynamic RAM memory cell comprises an MOS read transistor whose conductivity state is determined by the state of charge on a first electrode overlying the read transistor channel region. The first electrode is connected through a buried contact opening to a diffused region in the substrate. This diffusion serves as a junction isolated storage node. This storage node can be charged or discharged through an MOS write transistor. The first electrode is capacitively coupled to a field plate held at a first potential. A control gate formed in a second electrode controls conduction through the write transistor and also allows selective reading in an array of read transistors. Nondestructive read can be achieved together with transistor amplification of the charge stored on the first electrode.

REFERENCES:
IEEE Trans. Ed., vol. 26, #6, Jun. 1979, Chatterjee et al., "A Survey of High Density Dynamic Ram Cell Concepts".
IEDM Abstracts, 1980, (IEEE Publication), "A New Dynamic Ram Cell for VLSI Memories", Terada et al.

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