Highly scalable architecture for implementing switch fabrics...

Details Highly scalable architecture for implementing switch fabrics... Highly scalable architecture for implementing switch fabrics...

1999-07-02

2003-08-05

Yao, Kwang Bin (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

Reexamination Certificate

active

06603771

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to communication switching devices generally and, more particularly, to a highly scalable architecture for implementing switch fabrics with quality of services.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a block diagram of a circuit
10
is shown implementing a conventional crossbar switch fabric. A number of ports
12
a
-
12
n
are shown connected to a switch fabric
14
. The port
12
a
is shown comprising a serializer/deserializer block
16
, a storage buffer
18
, a scheduler
20
, a packet classifier
22
, a queue manager
24
, a packet classifier
26
, a queue manager
28
and a storage buffer
30
. Each of the ports
12
a
-
12
n
has similar components. A parallel bus
32
transmits data from the port
12
a
to the switch fabric
14
. Similarly, a parallel bus
34
receives data from the switch fabric
14
. A serial link
36
receives data from a line card (not shown) and a serial link
38
transmits data to the line card.
For the transmit side, the data arrives from the line card through the serial link
36
. The data is deserialized into parallel data by the serializer/deserializer circuit
16
and then presented to the packet classifier
22
. The packet classifier
22
looks at the information embedded within the packet data and determines the appropriate outgoing port
12
a
-
12
n
that will receive the packet data. The packet classifier
22
may also determine the priority of the packet data from the embedded information. The queue manager
24
informs the scheduler
20
about the new packet arrival. The packet is stored in the storage buffer
18
until the packet is scheduled to go to the appropriate port
12
a
-
12
n
through the switch fabric
14
. The scheduler
20
of each port
12
a
-
12
n
communicates with the port schedulers of the other ports
12
a
-
12
n
and, based a predetermined algorithm, schedules packets from all the incoming ports
12
a
-
12
n
to the outgoing ports
12
a
-
12
n
through the switch fabric
14
.
The packet classifier
22
and the queue manager
28
are normally implemented in an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Similarly, the scheduler
20
is normally implemented in an ASIC or an FPGA. The storage buffers
18
and
30
are normally implemented using dual port memories. The switch fabric
14
is a large pin count cross bar chip or is constructed using PLDs to implement a multiplexer function with control signals. The receive side has a similar operation provided by the packet classifier
26
, the queue manager
28
and the storage buffer
30
. However, the receive side only has to process priority information and not port information.
The performance of the circuit
10
is limited by the speed and width of the circuit
10
. To increase operating speed to a higher bandwidth requires either higher interface speed or an increased bus width of the switch fabric
14
. Additionally, this configuration requires a switch fabric chip
14
to connect ports for switching.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a plurality of interface circuits, a plurality of transmit outputs and a plurality of receive inputs. The plurality of interface circuits each comprises (i) a transmit circuit and (ii) a receive circuit. One of the plurality of transmit outputs is generally connected to one of the plurality of receive circuits. One of the plurality of receive inputs is generally connected to one of the plurality of transmit circuits. In general, each one of the plurality of the transmits outputs are generally connected to one of the plurality of the receive inputs.
The objects, features and advantages of the present invention include providing a communication interface that may (i) eliminate parallel interfaces from the system allowing more scalable solution, (ii) not require a separate switch fabric chip, (iii), be created by connecting the individual elements together, (iv) reduce the number of routes on the board which may reduce the board cost, (v) reduce the chip count for the system, and/or (vi) reduce power.


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