Highly pipelined bus architecture

Details Highly pipelined bus architecture Highly pipelined bus architecture

1996-07-29

1998-08-18

Sheikh, Ayaz R.

395561, 395468, 395473, G06F 1200, G06F 1300

Patent

active

057969779

ABSTRACT:
A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

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"The Metaflow Architecture", Val Popescu, Merle Schults, John Spracklen, Gary Gibson, Bruce Lightner and David Isaman, IEEE Micro, Jun. 1991 (pp. 10-13, 63-73).

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