Highly parallel switching systems utilizing error correction II

Details Highly parallel switching systems utilizing error correction II Highly parallel switching systems utilizing error correction II

2007-04-17

2007-04-17

Garber, Wendy R. (Department: 2612)

Communications: electrical

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Path selection

C340S002210

Reexamination Certificate

active

11074406

ABSTRACT:
An interconnection network has a first stage network and a second stage network and a collection of devices outside the network so that a first device is capable of sending data to a second device. The first stage network is connected to inputs of the second stage network. The first and second stage networks each have more outputs than inputs. The data is first sent from the first device to the first stage network and then from the first stage network to the second stage network. The data is sent to the second device from the second stage network. The number of inputs to a device from the second stage network exceeds the number of outputs from a device into the first stage network. The latency through the entire system may be a fixed constant.

REFERENCES:
patent: 6657998 (2003-12-01), Li
patent: 6754207 (2004-06-01), Hesse
patent: 6798744 (2004-09-01), Loewen et al.

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