Highly parallel cyclic redundancy code generator

Details Highly parallel cyclic redundancy code generator Highly parallel cyclic redundancy code generator

1995-10-06

1999-03-02

Moise, Emmanuel L.

Excavating

371 377, H03M 1300

Patent

active

058780572

ABSTRACT:
A highly parallel cyclic redundancy code generator has p precalculated k-bit remainder polynomials loaded in a lookup table. A cyclic redundancy code register has a p-bit portion and a k-bit portion. An input data message is input to an input XOR gate together with the contents of the p-bit portion to generate a p-bit result for storage in the p-bit portion. The content of the p-bit portion is used to control which k-bit remainder polynomials from the lookup table are to be parallel XOR'd to produce a partial cyclic redundancy code that is stored in the k-bit portion. The contents of the CRC register are shifted to the left and the process repeated until all of the bits of the input data message have been processed. The contents of the k-bit portion are then output as the CRC for the input data message.

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