Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2000-01-20
2001-12-18
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S118000
Reexamination Certificate
active
06331833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of analog-to-digital converters, and more specifically to such converters using sigma-delta (also known as delta-sigma) configurations.
2. Description of the Available Art
Converting analog signals to digital signals is accomplished using an analog-to-digital converter (ADC). An ADC circuit may contain a sigma-delta modulator circuit which is used to oversample an analog input signal. A decimation filter is required to follow the sigma-delta modulator circuit to filter and down-sample the digital output signal from the sigma-delta modulator to the Nyquist sample rate with minimal added in-band noise or distortion.
The standard topology for a sigma-delta A/D converter incorporates a low order analog-to-digital converter (ADC) to generate an output bitstream. This bitstream is sent both to a digital decimation filter to produce the final digital output, and to an input digital-to-analog converter (DAC) which, through a feedback loop, adjusts the subsequent output, based on the bitstream value.
The ADC is often implemented with a single comparator, taking the analog input and producing a single-bit digital output. This allows for a simple implementation of both A/D and D/A blocks. This approach becomes more difficult when designing a high order modulator because it is difficult to guarantee stability. This is due in part to overloading a single-bit comparator. As the input signal increases, the loop gain begins to drop rapidly and the system becomes unstable.
In order to avoid the instability associated with high order loops, multi-bit A/D and D/A architectures are normally used. This reduces the stability concerns associated with higher order loops because a system can be made with enough quantization levels such that overload will not occur and there is a graceful performance degradation as the modulator reaches saturation. Unfortunately this typically comes at the expense of a much more complex design, since it is difficult to achieve high linearity and low distortion from a simple multi-bit ADC. In contrast, a single bit ADC is linear by definition, eliminating much of the design effort of a multi-bit approach.
The linearity of an overall A/D conversion is no greater than the linearity of the internal blocks, namely the DAC and ADC. This is not a concern with a one-bit approach as these blocks are inherently linear. In order to stabilize higher order loops, several quantization levels may be required in these internal blocks. This requires a high level of control of the step size in the quantizer, as well as precise matching of components in the DAC which converts the digital output of the quantizer to an analog level added to the system input. Standard, inexpensive CMOS processes do not provide a ready solution to this problem as component matching capabilities are insufficient to achieve the desired linearity.
One available approach to this challenge has been to devise complex architectures to improve linearity beyond what is achievable with conventional design. This usually comes at the expense of more hardware on the integrated circuit.
There are several texts which generally describe sigma-delta data converters and refer to one-bit and multi-bit configurations of such converters. One such text is entitled: “Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation” by J. C. Candy and G. C. Temes, published by IEEE, January, 1992. Another such text is entitled: “Delta-Sigma Converters: Theory, Design and Simulation” by S. R. Norsworthy, R. Schreier and G. C. Temes, published by IEEE, November, 1996. Still another relevant text is entitled: “Analog-to-Digital and Digital-to-Analog Conversion Techniques” by D. F. Hoeschele, Jr., published by John Wiley & Sons, April, 1994 (Second Edition). The relevant content of these prior art publications is within the scope of information available to those having ordinary skill in the pertinent art and is hereby incorporated herein by reference as if fully set forth herein.
SUMMARY OF THE INVENTION
The disclosed invention eliminates much of the concern and expense of device matching by using a multi-bit architecture for the ADC and DAC, but implemented in such a way that during normal operation they behave like single-bit converters, thus sharing the high linearity and low distortion properties of simpler systems. When a high input signal is applied, a second bit is triggered and the system behaves like a more complex multi-bit system. This allows the system to remain stable where an available single-bit converter would overload and the system would become unstable.
The disclosed invention allows the high linearity of a single-bit architecture for the internal ADC and DAC of a sigma-delta data converter to be combined with the increased stability of a multi-bit converter. Graceful performance degradation compared to a single-bit system is also gained as the multi-bit system approaches saturation. Additionally, in a more traditional approach, the modulator coefficients are usually chosen rather conservatively to provide a margin of stability. This lowers the allowable input range for the modulator and thus lowers the achievable signal-to-noise ration (SNR). Since stability is better assured over a wider range of inputs with the inventive approach, the system may be designed to allow larger input signals and thus achieve higher peak signal-to-noise performance. Also, the inventive architecture allows for straightforward fabrication with a standard CMOS process, without the need for complex circuitry to achieve high linearity and low distortion.
During normal operation, an available sigma-delta converter is well within its operating range. Under these conditions a single-bit ADC and DAC are sufficient to remain stable, even with higher order converters. However, when the input is a large, sustained signal (relative to the full scale of the converter), the available single-bit approach is not sufficient to maintain system stability. Thus, in order to take advantage of the linearity of a single-bit approach while compensating for its shortfalls, the converter of the present invention provides a single-bit output during normal operation (that is, the higher order bit remains at logic low), and if the converter is close to its maximum or minimum range (implying a large positive or negative input signal) a second, higher-order bit is triggered. The trip point for the second bit need not be well controlled, as long as it is set outside the normal operation range, thereby simplifying the converter implementation and design. Thus, the second bit will fire during times of high amplitude input signal, insuring stability where the signal to noise ratio of a conventional converter would begin to drop off rapidly. Thus the present invention maintains stability without degrading system performance.
ADVANTAGES OF THE INVENTION
It is therefore a principal advantage of the invention to provide a sigma-delta analog-to-digital converter which operates as a single-bit converter for input analog signals within a selected range of operation and which operates as a multi-bit converter for input analog signals exceeding the selected range of operation.
It is another advantage of the invention to provide a sigma-delta analog-to-digital converter having the linearity of single bit operation during normal conditions when the analog signal input is within a maximum range and having triggered multi-bit operation during abnormal conditions when the analog signal input exceeds the maximum range.
It is still another advantage of the invention to provide a sigma-delta analog-to-digital converter that employs single-bit operation for nominal input signal conditions and triggers multi-bit operation for input signal overload conditions or near-overload conditions.
It is another advantage of the invention to provide an analog-to-digital converter having performance characteristics closer to the theoretically ideal signal-to-noise ratio than available conv
Hufford Michael M.
Lubkin Jeremy
Naviasky Eric H.
Cadence Design Systems Inc.
Crosby, Heafey Roach & May
Wamsley Patrick
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