Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Converting input voltage to output current or vice versa
Reexamination Certificate
2002-05-30
2003-06-24
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Converting input voltage to output current or vice versa
C327S065000, C330S254000
Reexamination Certificate
active
06583652
ABSTRACT:
BACKGROUND
1. Technical Field
This invention relates to analog circuits for converting an input voltage into an output current, and more particularly to programmable analog circuits for converting an input voltage into an output current.
2. Description of the Related Art
A transconductor is a circuit which receives an input voltage and generates an output current. The magnitude of the output current is proportional to the input voltage received, and the ratio by which the output current changes. The ratio of output current change to input voltage change is known as the conversion gain, or transconductance (G
m
=&Dgr;I
OUT
/&Dgr;V
IN
) of the transconductor. A differential transconductor receives a differential voltage impressed between two voltage input terminals, and generates a differential current between two current output terminals. The common-mode voltage of the two voltage input terminals is ignored.
A typical prior art differential transconductor art is shown in
FIG. 1. A
differential input voltage, V
INN
−V
INP
, is received between voltage input terminals
42
and
52
, and a corresponding differential output current is generated between current output terminals
48
and
58
. Current source circuit
30
includes current source
32
which delivers a current of magnitude I
0
into summing node
36
and current source
34
which delivers a current of magnitude I
0
into summing node
38
. Input circuit
40
, includes a gain block (e.g., operational amplifier (op-amp)
44
) having a non-inverting input coupled to the voltage input terminal
42
and an inverting input coupled to the summing node
36
. The output of op-amp
44
drives the gate of transistor
46
, which is a p-channel MOS transistor. Transistor
46
couples summing node
36
to current output terminal
48
. Similarly, a second input circuit
50
, includes an op-amp
54
having a non-inverting input coupled to voltage input terminal
52
and an inverting input coupled to summing node
38
. The output of op-amp
54
drives the gate of transistor
56
, which is also a p-channel MOS transistor. Transistor
56
couples summing node
38
to current output terminal
58
. Resistor
35
(having the value R) couples summing node
36
to summing node
38
. As is common with differential circuits, current source
32
and input circuit
40
are matched to current source
34
and input circuit
50
, respectively, to provide balanced differential operation.
The operation of this circuit can best be understood by looking initially at the left-most portion. Input circuit
40
functions to force the voltage of summing node
36
to follow input voltage, V
INN
, received on voltage input terminal
42
. This occurs because op-amp
44
drives the gate of transistor
46
to a suitable voltage such that the voltage of summing node
36
, which is coupled to the inverting input of op-amp
44
, follows the input voltage, V
INN
, coupled to the non-inverting input of op-amp
44
. For example, if the voltage of summing node
36
is too high, the output of op-amp
44
is driven lower, thus providing corrective gate drive to p-channel MOS transistor
46
. Consequently, a higher current flows through transistor
46
which lowers the voltage of summing node
36
until the voltage at summing node
36
is equal (or substantially equal) to the voltage at non-inverting input terminal of op-amp
44
. The right-most portion of the transconductor of
FIG. 1
operates in a similar fashion.
Thus, with the voltage of summing node
36
following input voltage V
INN
and the voltage of summing node
38
following input voltage V
INP
, the differential input voltage V
INN
−V
INP
is placed across resistor
35
, and causes a current I
S
of magnitude (V
INN
−V
INP
)/R to flow from summing node
36
to summing node
38
. If V
INP
is greater in magnitude than V
INN
then a negative current I
S
flows from summing node
36
to summing node
38
which is equivalent to a positive current flow from summing node
38
to summing node
36
.
Summing node
36
receives a current lo from current source
32
, and sources a current I
S
flowing into summing node
38
. Thus, the net current which is provided to the source of transistor
46
is I
0
−I
S
. The current, I
OUTN
, coupled to current output terminal
48
must also be equal to I
0
−I
S
because the sum of currents received into any node must equal zero. Similarly, summing node
38
receives current
10
from current source
34
, and receives a current I
S
flowing from summing node
36
. The net current received into summing node
38
is I
0
+I
S
, which is coupled by transistor
56
to the current output terminal
58
as I
OUTP
=I
0
+I
S
.
The topology of the circuit in
FIG. 1
is generally known as a degenerated pair linearized by servo-feedback, or a linearized resistor-based transconductor. The use of a resistor in setting the conversion gain of the transconductor generally results in high linearity, but also results in a conversion gain which is fixed by the choice of resistor value, and which varies with semiconductor process parameter variations. Consequently, programmable transconductors have been developed to allow selecting of the desired conversion gain after semiconductor manufacturing by, for example, a programmable resistor circuit.
An example of such a programmable transconductor can be found in U.S. Pat. No. 5,510,738, entitled “CMOS Programmable Resistor-Based Transconductor,” by James L. Gorecki and Yaohua Yang, (the “'738 patent”) which is incorporated herein by reference in its entirety.
FIG. 2
shows a programmable transconductor such as those disclosed in the '738 patent. In many aspects, the programmable transconductor of
FIG. 2
is similar to the transconductor of FIG.
1
. Input circuit
40
includes an op-amp
44
(functioning as a gain block) having a non-inverting input coupled to voltage input terminal
42
and an inverting input coupled to first feedback node
60
. The output of op-amp
44
drives the gate of transistor
46
, which couples summing node
36
to current output terminal
48
. Similarly, input circuit
50
includes op-amp
54
having a non-inverting input coupled to voltage input terminal
52
and an inverting input coupled to a feedback node
70
. The output of op-amp
54
drives the gate of transistor
56
, which couples summing node
38
to the current output terminal
58
.
In further contrast to the transconductor of
FIG. 1
, the programmable transconductor of
FIG. 2
includes circuit
37
A having an array of switch circuits (
62
,
64
,
66
,
72
,
74
, and
76
) and including a resistor circuit having a total resistance of R coupling summing node
36
to summing node
38
. The resistor circuit includes resistors
63
,
65
,
69
,
75
, and
73
connected in series and defining a group of intermediate nodes
67
,
68
,
78
, and
77
respectively therebetween. These intermediate nodes, together with summing nodes
36
and
38
, form a group of tap nodes of the resistor circuit.
Switch circuits
62
,
64
, and
66
couple summing node
36
to feedback node
60
when enabled by logical signals S
3
, S
2
, and S
1
, respectively. Switch circuits
72
,
74
, and
76
couple summing node
38
to feedback node
70
when enabled by logical signals S
3
, S
2
, and S
1
, respectively. Logical signals S
1
, S
2
, and S
3
are preferably digital control signals which select the desired transconductance of the circuit, but may also be a hardwired or some other fixed connection.
In operation, the programmable transconductor of
FIG. 2
can be understood by assuming (for example) that logical signal S
2
is active, and thus switch circuits
64
and
74
are enabled and remaining switch circuits
62
,
66
,
72
, and
76
are disabled. Since intermediate node
67
is coupled to feedback node
60
which is coupled to the inverting input of op-amp
44
, input circuit
40
functions to force the voltage of feedback node
60
and intermediate node
67
to follow the voltage V
INN
, received on voltage input
Hildebrant Paul
Klein Hans W.
Li Jian
Ascolese Marc R.
Campbell Stephenson Ascolese LLP
Lattice Semiconductor Corporation
Tran Toan
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