Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1997-06-30
2001-06-12
Ton, Dang (Department: 2732)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395430, C370S412000
Reexamination Certificate
active
06246680
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the field of computer networking devices. More particularly, the invention relates to an architecture for a highly integrated network element building block.
BACKGROUND OF THE INVENTION
An increasing number of users are requiring increased bandwidth from existing networks due to multimedia applications for accessing the Internet and World Wide Web, for example. Therefore, future networks must be able to support a very high bandwidth and a large number of users. Furthermore, such networks should be able to support multiple traffic types such as data, voice, and video which typically require different bandwidths.
Statistical studies indicate that the network domain, i.e., a group of interconnected local area networks (LANs), as well as the number of individual end-stations connected to each LAN, will grow at ever increasing rates in the future. Thus, more network bandwidth and more efficient use of resources is needed to meet these requirements.
Building networks using Layer
2
elements such as bridges provides fast packet forwarding between LANs; however there is no flexibility in traffic isolation, redundant topologies, and end-to-end policies for queuing and access control. While the latter attributes may be met using Layer
3
elements such as routers, packet forwarding speed is sacrificed in return for the greater intelligence and decision making capabilities provided by routers.
Therefore, it is desirable to provide a cost-effective, high performance network device building block that is capable of performing non-blocking wire-speed multi-layer switching on N ports. Generally, it would be advantageous to provide a network device building block that linearly scales its performance with advances in silicon technology. Therefore, it is desirable to share common resources, centralize common processing, and maximize the utilization of hardware resources. More specifically, it is desirable to utilize a dynamic packet memory management scheme to facilitate sharing of a common packet memory among all input/output ports for packet buffering. Also, it is desirable to centralize packet header processing and to provide efficient access to a centralized database for multiple protocol layer based forwarding decisions. Further, it would be advantageous to provide a central processing unit (CPU) interface that requests forwarding decisions of a switch fabric for CPU originated packets in a first packet forwarding mode and bypasses the switch fabric header matching by transferring the packet directly to one or more specified ports in a second packet forwarding mode.
SUMMARY OF THE INVENTION
A method and apparatus for packet forwarding and filtering is described in the context of an architecture for a highly integrated network element building block. According to one aspect of the present invention, a network device building block includes a network interface with multiple ports for transmitting and receiving packets over a network. The network device building block also includes a packet buffer storage which is coupled to the network interface. The packet buffer storage acts as an elasticity buffer for adapting between incoming and outgoing bandwidth requirements. The network device building block further includes a switch fabric which is coupled to the network interface. The switch fabric provides forwarding decisions for received packets. A given forwarding decision includes a list of ports upon which a particular received packet is to be forwarded. A central processing unit (CPU) interface is also included in the network device building block. The CPU interface is coupled to the switch fabric and is configured to forward packets received from the CPU based upon forwarding decisions provided by the switch fabric.
According to another aspect of the present invention, a switch element includes a switch fabric configured to generate forwarding decisions for received packets. The switch element also includes multiple interfaces for receiving and transmitting packets. Each of the interfaces are coupled in communication with the switch fabric for requesting and receiving forwarding decisions. The interfaces include a network interface, a cascading interface, and a central processing unit (CPU) interface. The network interface further includes multiple external ports for communication with devices on a network. At least two internal links are provided by the cascading interface for interconnecting with one or more other switch elements in a full-mesh topology. The CPU interface allows communication of packets and commands between the switch fabric and a CPU. The switch element further includes a shared memory manager which is coupled to the interfaces for dynamically allocating and deallocating buffers in a shared buffer memory on behalf of the interfaces. The shared memory manager further tracks the status of buffers in the shared buffer memory.
Other features of the present invention will be apparent from the accompanying drawings and from the detailed description which follows.
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Frazier Howard
Hendel Ariel
Muller Shimon
Blakely & Sokoloff, Taylor & Zafman
Sam Phirin
Sun Microsystems Inc.
Ton Dang
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