Highly integrated, high-speed, low-power serdes and systems

Details Highly integrated, high-speed, low-power serdes and systems Highly integrated, high-speed, low-power serdes and systems

2007-08-30

2010-12-07

Sheikh, Ayaz R (Department: 2476)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S907000

Reexamination Certificate

active

07848367

ABSTRACT:
High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A serializer may include a serdes framer interface (SFI) circuit, a clock multiplier unit, and a multiplexing circuit. A deserializer may include an input receiver circuit for receiving and adjusting an input data signal, a clock and data recovery circuit (CDR) for recovering clock and data signals, a demultiplexing circuit for splitting one or more data channels into a higher number of data channels, and a serdes framer interface (SFI) circuit for generating a reference channel and generating output data channels to be sent to a framer. The input receiver circuit may include a limiting amplifier. Each of the serializer and deserializer may further include a pseudo random pattern generator and error checker unit. The serializer and deserializer each may be integrated into its respective semiconductor chip or both may be integrated into a single semiconductor chip.

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