Highly-integrated flash memory and mask ROM array architecture

Details Highly-integrated flash memory and mask ROM array architecture Highly-integrated flash memory and mask ROM array architecture

2005-01-04

2005-01-04

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S104000, C365S185330

Reexamination Certificate

active

06839278

ABSTRACT:
A memory device is achieved. The memory device comprises an array of Flash cells and mask ROM cells in a common substrate. Each Flash cell comprises a floating gate, a control gate, a source, a drain, and a channel. Each mask ROM cell comprises a gate, a source, a drain, and a channel. Each source of the mask ROM cells is shared with one Flash cell source. Each electrode of each mask ROM cell gate is coupled to at least one Flash cell control gate. The mask ROM cell gate electrodes comprise a common layer with electrodes of the Flash cell control gates. The mask ROM cells lie in spaces between the Flash cells in the array.

REFERENCES:
patent: 5666304 (1997-09-01), Hikawa et al.
patent: 5793678 (1998-08-01), Kato et al.
patent: 5844270 (1998-12-01), Kim et al.
patent: 5986933 (1999-11-01), Takeuchi et al.

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