Patent
1989-07-07
1990-12-04
Hille, Rolf
357 74, H01L 2312, H01L 2304
Patent
active
049757652
ABSTRACT:
In a highly integrated circuit the semiconductor chip (8) is fastened on a substrate (17) which projects on all sides only a few millimeters beyond the semiconductor chip (8). For Full dynamic testing of the circuit before insertion, connections are provided which are arranged outside the projecting substrate edge (23) with a sufficiently large grid spacing.
In a first embodiment (FIG. 2D) "lost" test connections (5) are used which are separated after testing.
In a second embodiment (FIG. 3E), contact areas in the form of bumps (21) are used for testing which are arranged on the underside of the through-holes (18) lying in the chip mounting area.
In this manner it is possible to realize a circuit with greatly reduced space requirement, which at the same time can be fully tested dynamically before insertion.
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patent: 4701781 (1987-10-01), Sankhagowit
Patent Abstracts of Japan, vol. 5, No. 159 (E-77) (831), Oct. 14, 1981 & JP, A, 56-88343.
Electronics, Nov. 11 (1985), pp. 26-31, "Japan's Packaging Goes World Class", Charles L. Cohen.
Electronic Packaging & Production, Dec. 1984, pp. 34-39, "Tab Technology Tackles High Density Interconnections".
Ackermann Karl-Peter
Berner Gianni
Clark S. V.
Contraves AG
Hille Rolf
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