Highly integrated and reliable DRAM adapted for self-aligned...

Details Highly integrated and reliable DRAM adapted for self-aligned... Highly integrated and reliable DRAM adapted for self-aligned...

1997-06-16

2002-02-05

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S296000, C438S622000, C438S791000

Reexamination Certificate

active

06344692

ABSTRACT:

BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture, and more particularly to a semiconductor device and its manufacture suitable for highly integrated and reliable DRAMs (Dynamic Random Access Memories).
b) Description of the Related Art
As the capacity of DRAM becomes large, it becomes essential to make its fundamental constituent, a memory cell, more finer in order to realize high integration and low cost.
A general DRAM cell is constituted of one MOS transistor and one capacitor. In order to make a memory cell finer, it is therefore substantial that how a large capacitance is obtained from a small cell size.
As a method of procuring a capacitance of a memory cell, a trench type cell and a stack type cell have recently been proposed and adopted as the cell structure of current DRAMs. A trench type cell has a capacitor formed in a trench in the substrate. A stack type cell has a capacitor three-dimensionally stacked above the MOS transistor.
More improved cell structures have also been proposed, particularly for stack type cells, such as a fin type cell and a cylinder type cell. A fin type cell has a plurality of storage electrodes disposed generally in parallel with the substrate and the upper and lower surfaces of each storage electrode are used as capacitor electrodes so that the capacitance per unit area occupied by a cell can be increased more than a stack type cell. A cylinder type cell has a cylindrical storage electrode disposed generally vertically to the substrate to increase the capacitance.
By using these cell structures and their manufacture processes, it becomes possible to realize DRAMs of 64 Mbit class with 0.35 &mgr;m design rule.
However, these technologies only are insufficient for higher integration such as DRAMs of 256 Mbit and 1 Gbit class with 0.25 &mgr;m to 0.15 &mgr;m design rule.
It is therefore necessary not only to reduce a substrate area occupied by a capacitor but to make as small as possible an alignment margin set for eliminating troubles to be caused by wiring shortages or the like during photolithography. It is also necessary to solve the problems associated with improved cell structures such as a cylinder type cell.
A first problem pertains to alignment.
A self align contact (SAC) method is already known as a method of forming a fine contact window. This method is disclosed, for example, in Japanese Patent Laid-open Publication No. 58-115859.
With this method, a first insulating film is formed on a gate electrode layer of a MOS transistor and patterned to form a gate electrode. After source/drain diffusion regions are formed, a second insulating film is formed and etched through anisotropic etching until the diffusion regions are exposed. Since an insulating film is formed on the side wall of a gate electrode portion including the first insulating film, the periphery of the gate electrode can be perfectly insulated with the first and second insulating films. Contact window areas can also be formed above the diffusion regions in a self alignment manner.
If the self align method is used for forming contact windows as described above, an alignment margin is not necessary between the underlying conductive layers (gate electrode and source/drain diffusion regions) and contact windows. The cell can be made fine correspondingly because the alignment margin is not necessary. Such a simple self align method is still unsatisfactory because multi-layer processes are used for making highly integrated DRAM cells finer.
An example of improved self align contact techniques used for DRAM cells will be described with reference to schematic cross sectional views of
FIG. 34A
to
35
B which illustrate manufacture processes.
FIGS. 34A and 34B
and
FIGS. 35A and 35B
are cross sectional views of typical memory cell units taken along the direction crossing the word line direction (along the direction of source/drain of MOS transistors). With reference to these drawings, a method of forming contact windows by using the self-align contact technique will be described specifically, the contact windows being used for contact between each of bit lines and storage electrode with the source/drain diffusion region of the MOS transistor.
First, as shown in
FIG. 34A
, a gate insulating film
113
is formed on a silicon substrate
111
surrounded by a LOCOS oxide film
112
. On this gate insulating film
113
, a polysilicon layer
114
and a tungsten silicide layer
115
are deposited to form a polycide gate electrode. Source/drain regions
116
are formed on both sides of the gate electrode. A nitride film
117
is formed surrounding the periphery of the polycide gate electrode which corresponds to the word line.
The processes up to this are the same as the above-described self align contact method so that these processes can be executed in accordance with the method described in the Japanese Patent Laid-open Publication No. 58-115859.
Next, a silicon oxide film
118
is formed over the whole surface of the nitride film
117
. The silicon oxide film
118
is planarized by chemical mechanical polishing (CMP) or the like to facilitate the succeeding processes.
Next, as shown in
FIG. 34B
, on the planarized oxide film
118
, a resist layer is coated and patterned by usual photolithography to form a resist pattern
119
to be used as an etching mask.
Next, as shown in
FIG. 35A
, by using the resist pattern
119
as a mask, the oxide film
118
is etched to form contact windows
120
reaching the diffusion regions
116
. In this case, the etching conditions of the oxide film are set so as to have a large etching selection ratio of the oxide film to the silicon nitride film. Therefore, even if the nitride film
117
is exposed while etching the oxide film, the nitride film is not etched so much and the areas generally the same as those of the self align contact windows first formed in the nitride film become new contact windows.
Next, the resist pattern
119
is removed by known techniques.
Then, as shown in
FIG. 35B
, a conductive layer
121
is formed on the contact windows.
With the above method, even if the contact windows are formed above or near the gate electrode because of displacement of the resist pattern
119
, the conductive layer
121
and polycide electrode are not electrically short-circuited. Therefore, it is not necessary to have an alignment margin of the contact window relative to the polycide electrode.
According to this technique, contact windows can be formed in a self alignment manner, while planarizing the oxide film
118
serving as an interlayer insulating film.
Such self align contact (SAC) technique will be called hereinafter “nitride film spacer SAC”.
The following problems occur when nitride spacer SAC is used.
One problem associated with the gate electrode structure formed by nitride film spacer SAC is the deteriorated transistor characteristics.
The problems of the gate electrode structure using a nitride film spacer side wall are described, for example, in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 3 MARCH 1991 “Hot-Carrier Injection Suppression Due to the Nitride-Oxide LDD Spacer Structure”, T. Mizumo et. al.
This paper describes that as compared to a MOS transistor with an oxide film side wall, the electrical characteristics of a MOS transistor with a nitride film side wall are deteriorated greatly, for example, in the hot carrier effects, leading to a lower reliability. This may be ascribed to a larger number of traps in a silicon nitride film than in an oxide film.
The above paper discloses a method of preventing deterioration of transistor characteristics by forming an oxide film between the nitride film side wall and gate electrode and between the nitride film side wall and substrate so as to suppress the influence of the nitride film.
However, such a structure cannot be applied directly to the nitride film spacer SAC structure.
This problem will be explained with reference to
FIGS. 36A
to
37
. Similar to
FIGS. 34A and 34B
and
FIGS. 35A and 3

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