Highly-efficient time-division data multiplexing apparatus

Multiplex communications – Wide area network – Packet switching

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370112, 307244, H04J 316

Patent

active

053115171

ABSTRACT:
A time-division data multiplexing apparatus has first through Nth memories for temporarily storing first through Nth data blocks, and first through Nth address control circuits for controlling the first through Nth memories, respectively. Any nth address control circuit (n=1,2, . . . , N) calculates a time period A.sub.n of an nth time slot to be assigned to an nth data block from a data size M.sub.n of the nth data block stored in an nth memory and an available time period, T.sub.n indicated by an available time signal as a time period available for transmission of the nth through Nth data blocks, and controls the nth memory so as to read out data of the nth data block stored in the nth memory for A.sub.n while outputting for A.sub.n an selection signal S.sub.n indicating that the data stored in the nth memory is being read out. A selector coupled to the memories is responsive to the nth selection signal for selectively outputting the nth data block from the nth memory to form a time-division multiplexed data. Any nth address control circuit (n=1, 2, . . . , N-1) calculates a difference between T.sub.n and A.sub.n, and giving an (n+1)th address control circuit with the difference as a signal indicative of a time period T.sub.n+1 available for transmission of the (n+1)th through Nth data blocks.

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Technology of PCM Communications, Kaneko, Sanpo Publishing Co., 1983, pp. 10-13.

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