Highly configurable PLL architecture for programmable logic

Details Highly configurable PLL architecture for programmable logic Highly configurable PLL architecture for programmable logic

2006-08-29

2006-08-29

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

07098707

ABSTRACT:
A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

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Stratix Programmable Logic Device Family Data Sheet, Altera Corporation, Feb. 2002, pp. 76-104.

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