Highly compact non-volatile memory and method therefor with...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S189050, C365S189120

Reexamination Certificate

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06940753

ABSTRACT:
A non-volatile memory device capable of reading and writing a large number of memory cells in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. In one aspect, data latches associated with the multiple read/write circuits are I/O enabled and coupled in a compact manner for storage and serial transfer. They are implemented by one or more chain of link modules, which can selectively behave as inverters or latches. A method enables the use of a minimum number of link modules by cycling data between a set of master link modules and a substantially smaller set of slave link modules.

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Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
U. Tietze-CH. Schenk: “Halbleiterschaltungstechnik,” 1974, Springer-Verlag, Berlin; XP002267743; paragraph 18.6, 3 pages (translated).

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